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公开(公告)号：US20230188317A1
公开(公告)日：2023-06-15
申请号：US17888836
申请日：2022-08-16
申请人： Samsung Electronics Co., Ltd. , Seoul National University R&DB Foundation , Industry Academic Cooperation Foundation, Chosun University , Daegu Gyeongbuk Institute of Science and Technology
发明人： Woosuk CHOI , Joon-Woo LEE , Eunsang LEE , Young-Sik KIM , Yongjune KIM , Jong-Seon NO , Junghyun LEE
IPC分类号： H04L9/00
摘要： An apparatus includes: one or more processors configured to: generate packed data by performing data packing on an encrypted image; and perform a homomorphic encryption operation based on the packed data and a weight.
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公开(公告)号：US20240106632A1
公开(公告)日：2024-03-28
申请号：US18521187
申请日：2023-11-28
申请人： Samsung Electronics Co., Ltd. , Seoul National University R&DB Foundation , Industry Academic Cooperation Foundation, Chosun University
发明人： Jong-Seon NO , Yongwoo LEE , Young-Sik KIM
CPC分类号： H04L9/0825 , G06F7/523 , G06F7/766 , G06F17/16 , H04L9/008 , H04L9/0618
摘要： A processor-implemented method with homomorphic encryption includes: receiving a first ciphertext corresponding to a first modulus; generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation.
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公开(公告)号：US20200044669A1
公开(公告)日：2020-02-06
申请号：US16599648
申请日：2019-10-11
发明人： Sang-Uhn CHA , Ye-Sin RYU , Young-Sik KIM , Su-Yeon DOO
摘要： An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
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公开(公告)号：US20220271922A1
公开(公告)日：2022-08-25
申请号：US17516924
申请日：2021-11-02
申请人： Samsung Electronics Co., Ltd. , Seoul National University R&DB Foundation , Industry Academic Cooperation Foundation, Chosun University
发明人： Jong-Seon NO , Yongwoo LEE , Young-Sik KIM
摘要： A processor-implemented method with homomorphic encryption includes: receiving a first ciphertext corresponding to a first modulus; generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation.
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5.发明申请公开(公告)号：US20210351912A1
公开(公告)日：2021-11-11
申请号：US17192162
申请日：2021-03-04
申请人： SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION , Industry-Academic Cooperation Foundation, Chosun University
发明人： Jung-Seon NO , Joonwoo LEE , Young-Sik KIM , Youngwoo LEE , Eunsang LEE
IPC分类号： H04L9/00
摘要： An encryption method and apparatus based on homomorphic encryption using an odd function property. The encryption method includes generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on an odd function property for a modulus corresponding to the ciphertext.
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公开(公告)号：US20210351913A1
公开(公告)日：2021-11-11
申请号：US17218790
申请日：2021-03-31
申请人： Samsung Electronics Co., Ltd , SNU R&DB FOUNDATION , Industry-Academic Cooperation Foundation, Chosun University
发明人： Jong-Seon NO , Joonwoo LEE , Young-Sik KIM , Yongwoo LEE , Eunsang LEE
IPC分类号： H04L9/00
摘要： Disclosed is an encryption method and apparatus. The encryption method using homomorphic encryption may include generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on a selection of one or more target points for a modulus corresponding to the ciphertext.
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公开(公告)号：US20150279787A1
公开(公告)日：2015-10-01
申请号：US14673852
申请日：2015-03-30
发明人： Doo-Jin KIM , Young-Sik KIM , Tea-Seog UM , Yong-Dae HA
IPC分类号： H01L23/544 , H01L25/00 , H01L25/07
CPC分类号： H01L23/544 , H01L21/67144 , H01L21/6836 , H01L25/074 , H01L25/50 , H01L2221/68354 , H01L2221/68381 , H01L2223/54426 , H01L2223/54486 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/73265 , H01L2225/06562 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.
摘要翻译： 提供了一种对准引导件，包括对准引导件的半导体封装以及包括对准引导件的半导体封装的制造方法。 半导体封装可以包括安装在电路板上的电路板和对准引导件。 对准引导件可以具有多个阶梯部分。 多个半导体芯片可以堆叠在电路板上并与对准引导件的阶梯部分接合。 根据所公开的半导体封装，可以以高精度和足够的余量堆叠大量的半导体芯片。 因此，可以降低芯片堆叠过程中的故障率和缺陷，并且可以提高半导体封装的可靠性和稳定性。
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