公开(公告)号：US20240038295A1

公开(公告)日：2024-02-01

申请号：US18348591

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G11C11/4096 ,  H01L25/065 ,  H10B80/00 ,  H01L23/00 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  G11C11/4076 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2924/14361 ,  H01L2224/06135

Abstract: A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

公开(公告)号：US11587598B2

公开(公告)日：2023-02-21

申请号：US17385002

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdo Um ,  Younghoon Son ,  Youngdon Choi ,  Jindo Byun ,  Hyunyoon Cho ,  Junghwan Choi

IPC: H04B1/00 ,  G11C7/10 ,  H04L25/49

Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

公开(公告)号：US20230418488A1

公开(公告)日：2023-12-28

申请号：US18243350

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F3/06 ,  G11C7/10 ,  H04L25/49

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/10 ,  H04L25/4917 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1051 ,  G11C2207/2254 ,  H03M5/02

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

公开(公告)号：US20220076716A1

公开(公告)日：2022-03-10

申请号：US17385002

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdo Um ,  Younghoon Son ,  Youngdon Choi ,  Jindo Byun ,  Hyunyoon Cho ,  Junghwan Choi

IPC: G11C7/10

Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

公开(公告)号：US20230342050A1

公开(公告)日：2023-10-26

申请号：US18304813

申请日：2023-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0611 ,  G06F3/0673

Abstract: Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

公开(公告)号：US11782618B2

公开(公告)日：2023-10-10

申请号：US17239592

申请日：2021-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/10 ,  H04L25/49 ,  G06F3/06 ,  H03M5/02

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H04L25/4917 ,  G11C2207/2254 ,  H03M5/02

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

公开(公告)号：US20220083244A1

公开(公告)日：2022-03-17

申请号：US17239592

申请日：2021-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F3/06 ,  G11C7/10 ,  H04L25/49

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.