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公开(公告)号：US11594267B2
公开(公告)日：2023-02-28
申请号：US17230403
申请日：2021-04-14
发明人： Mingyu Lee , Jaewoo Park , Younghoon Son , Youngdon Choi , Hyungmin Jin , Junghwan Choi
摘要： A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.
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公开(公告)号：US11587598B2
公开(公告)日：2023-02-21
申请号：US17385002
申请日：2021-07-26
发明人： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
摘要： A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.
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公开(公告)号：US20220076715A1
公开(公告)日：2022-03-10
申请号：US17347998
申请日：2021-06-15
发明人： Sucheol Lee , Younghoon Son , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC分类号： G11C7/10 , H03K19/017 , H03K7/02
摘要： A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.
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公开(公告)号：US20220075725A1
公开(公告)日：2022-03-10
申请号：US17320460
申请日：2021-05-14
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G06F12/0802 , G11C7/10 , H03K19/00 , G11C8/06 , H03K19/0185
摘要： A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.
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公开(公告)号：US11587609B2
公开(公告)日：2023-02-21
申请号：US17228943
申请日：2021-04-13
发明人： Kwangseob Shin , Jaewoo Park , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C11/4093 , G06F13/16 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C7/10 , G11C29/42 , G11C5/14 , G11C7/06 , G11C7/22 , G11C8/10 , H04L25/02
摘要： A multi-level signal receiver includes a data sampler having (M−1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M−1) reference voltages, to thereby generate (M−1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M−1) sense amplifiers by: (i) adjusting at least one of (M−1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals, where each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.
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公开(公告)号：US20220091158A1
公开(公告)日：2022-03-24
申请号：US17308974
申请日：2021-05-05
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
摘要： A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.
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7.发明申请公开(公告)号：US20220083244A1
公开(公告)日：2022-03-17
申请号：US17239592
申请日：2021-04-24
发明人： Youngdo Um , Jaewoo Park , Younghoon Son , Youngdon Choi , Junghwan Choi
摘要： A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.
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公开(公告)号：US20220059156A1
公开(公告)日：2022-02-24
申请号：US17321678
申请日：2021-05-17
发明人： Junyoung Park , Younghoon Son , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC分类号： G11C11/4093 , G11C11/4076 , G06F13/16
摘要： In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
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公开(公告)号：US11615833B2
公开(公告)日：2023-03-28
申请号：US17223458
申请日：2021-04-06
发明人： Kwangseob Shin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C16/26 , G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4099
摘要： A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.
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公开(公告)号：US11521672B2
公开(公告)日：2022-12-06
申请号：US17230519
申请日：2021-04-14
发明人： Hyeokjun Choi , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C7/22 , G11C11/4091 , G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4096
摘要： A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.
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