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1.发明公开公开(公告)号：US20230409496A1
公开(公告)日：2023-12-21
申请号：US18242034
申请日：2023-09-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin JIN , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G06F13/1668 , H04L25/4917
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号：US20230253018A1
公开(公告)日：2023-08-10
申请号：US18134618
申请日：2023-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Park , Jaewoo Park , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G11C5/147 , G11C7/1063 , G11C7/1069 , G11C7/109 , G11C7/1096 , G11C11/565 , H04L25/028 , H04L25/4917 , G11C2207/101
Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
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公开(公告)号：US11657859B2
公开(公告)日：2023-05-23
申请号：US17732220
申请日：2022-04-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunyoon Cho , Sukhee Cho , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G11C7/1072 , G11C7/109 , G11C7/1045 , G11C7/1063 , G11C7/14
Abstract: A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.
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公开(公告)号：US11594267B2
公开(公告)日：2023-02-28
申请号：US17230403
申请日：2021-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mingyu Lee , Jaewoo Park , Younghoon Son , Youngdon Choi , Hyungmin Jin , Junghwan Choi
Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.
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公开(公告)号：US11693030B2
公开(公告)日：2023-07-04
申请号：US17308974
申请日：2021-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G01R1/203 , G01R1/06766 , G01R31/2601
Abstract: A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.
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Patent Agency Ranking
公开(公告)号：US11587598B2
公开(公告)日：2023-02-21
申请号：US17385002
申请日：2021-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.
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公开(公告)号：US20220076715A1
公开(公告)日：2022-03-10
申请号：US17347998
申请日：2021-06-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sucheol Lee , Younghoon Son , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC: G11C7/10 , H03K19/017 , H03K7/02
Abstract: A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.
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公开(公告)号：US20220075725A1
公开(公告)日：2022-03-10
申请号：US17320460
申请日：2021-05-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC: G06F12/0802 , G11C7/10 , H03K19/00 , G11C8/06 , H03K19/0185
Abstract: A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.
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公开(公告)号：US11789879B2
公开(公告)日：2023-10-17
申请号：US17903240
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G06F13/1668 , H04L25/4917
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号：US11657860B2
公开(公告)日：2023-05-23
申请号：US17361780
申请日：2021-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joohwan Kim , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G11C7/1084 , G06F3/0656 , G06F3/0679 , G11C7/222
Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.
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