公开(公告)号：US20240395298A1

公开(公告)日：2024-11-28

申请号：US18794825

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US20240202067A1

公开(公告)日：2024-06-20

申请号：US18223124

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeog CHOI ,  Changkyu Seol ,  Dong Kim ,  Inhoon Park ,  Jinsoo Lim ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.

公开(公告)号：US20230409496A1

公开(公告)日：2023-12-21

申请号：US18242034

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungmin JIN ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F13/16 ,  H04L25/49

CPC classification number: G06F13/1668 ,  H04L25/4917

Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

公开(公告)号：US11757567B2

公开(公告)日：2023-09-12

申请号：US17590474

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Jiyoup Kim ,  Hyejeong So ,  Myoungbo Kwak ,  Pilsang Yoon ,  Sucheol Lee ,  Jinsoo Lim ,  Youngdon Choi

IPC: H04L1/00 ,  G06F1/03

CPC classification number: H04L1/0041 ,  G06F1/03 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0084

Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

公开(公告)号：US20230253018A1

公开(公告)日：2023-08-10

申请号：US18134618

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Park ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C5/14 ,  G11C7/10 ,  G11C11/56 ,  H04L25/02 ,  H04L25/49

CPC classification number: G11C5/147 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/1096 ,  G11C11/565 ,  H04L25/028 ,  H04L25/4917 ,  G11C2207/101

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

公开(公告)号：US11687114B2

公开(公告)日：2023-06-27

申请号：US17145211

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Park ,  Young-Hoon Son ,  Hyun-Yoon Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F1/06 ,  G11C11/406 ,  G11C11/403 ,  G06F13/40

CPC classification number: G06F1/06 ,  G06F13/4022 ,  G11C11/403 ,  G11C11/40607

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

公开(公告)号：US11657859B2

公开(公告)日：2023-05-23

申请号：US17732220

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunyoon Cho ,  Sukhee Cho ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1072 ,  G11C7/109 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/14

Abstract: A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.

公开(公告)号：US11627021B2

公开(公告)日：2023-04-11

申请号：US17563406

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi ,  Changsik Yoo

IPC: H04L25/02 ,  H04L25/14 ,  H04L25/49

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

公开(公告)号：US11594267B2

公开(公告)日：2023-02-28

申请号：US17230403

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu Lee ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Hyungmin Jin ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16

Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

公开(公告)号：US20240406041A1

公开(公告)日：2024-12-05

申请号：US18422058

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Choi ,  Jaeha Kim ,  Meyong Su Ko ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

IPC: H04L25/06 ,  H04L1/1867

Abstract: A receiver for receiving a data signal, comprising, an analog-to-digital converter configured to convert the data signal into digital data, a first-in-first-out buffer configured to determine a frame boundary of the digital data by referring to a comma index to output the digital data in units of data frames according to the determined frame boundary, a decision feedback equalizer configured to process a data frame output from the first-in-first-out buffer through a decision feedback equalization operation, wherein feedback data used in the decision feedback equalization operation of the data frame uses a predetermined fixed pattern, and a comma detector configured to generate the comma index by comparing a determined value of the data frame with the predetermined fixed pattern. The data frame may include a preceding data field in which a message is stored and a subsequent comma field having the same bit value as the fixed pattern.