公开(公告)号：US20220230666A1

公开(公告)日：2022-07-21

申请号：US17404510

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TONGSUNG KIM ,  YOUNGMIN JO ,  MANJAE YANG ,  CHIWEON YOON ,  JUNHA LEE ,  BYUNGHOON JEONG

IPC: G11C7/22 ,  G06F3/06

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US20240379141A1

公开(公告)日：2024-11-14

申请号：US18781289

申请日：2024-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TONGSUNG KIM ,  YOUNGMIN JO ,  MANJAE YANG ,  CHIWEON YOON ,  JUNHA LEE ,  BYUNGHOON JEONG

IPC: G11C7/22 ,  G06F1/04 ,  G06F3/06 ,  G11C5/14 ,  G11C29/02

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US20210027827A1

公开(公告)日：2021-01-28

申请号：US16822164

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS co., LTD.

Inventor： HWAPYONG KIM ,  HUNDAE CHOI ,  JUNHA LEE

IPC: G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  H03K19/00

Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.