公开(公告)号：US20210391351A1

公开(公告)日：2021-12-16

申请号：US16901091

申请日：2020-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takuma TAKIMOTO ,  Masayuki HIROI ,  Akira INOUE

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11565 ,  G11C16/16

Abstract: A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.

公开(公告)号：US20200295012A1

公开(公告)日：2020-09-17

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/768

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200091157A1

公开(公告)日：2020-03-19

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.