公开(公告)号：US20240194262A1

公开(公告)日：2024-06-13

申请号：US18354325

申请日：2023-07-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takayuki MAEKURA ,  Takaaki IWAI ,  Hiroyuki OGAWA

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

公开(公告)号：US20220157842A1

公开(公告)日：2022-05-19

申请号：US16951354

申请日：2020-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Shinsuke YADA ,  Mitsuteru MUSHIGA ,  Akio NISHIDA ,  Hiroyuki OGAWA ,  Teruo OKINA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

公开(公告)号：US20190355663A1

公开(公告)日：2019-11-21

申请号：US15982215

申请日：2018-05-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Akio NISHIDA ,  Murshed CHOWDHURY ,  Takahito FUJITA ,  Kiyokazu SHISHIDO ,  Hiroyuki OGAWA

IPC: H01L23/532 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

公开(公告)号：US20190057741A1

公开(公告)日：2019-02-21

申请号：US15780607

申请日：2016-12-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Fumiaki Toyama ,  Takuya Ariki

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11575 ,  G11C5/02 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L27/1157 ,  G11C8/10

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

公开(公告)号：US20170358593A1

公开(公告)日：2017-12-14

申请号：US15176674

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Zhenyu LU ,  Alexander CHU ,  Kensuke YAMAGUCHI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Yan LI ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

公开(公告)号：US20170236746A1

公开(公告)日：2017-08-17

申请号：US15274451

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Zhenyu LU ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Sung Tae LEE ,  Yao-sheng LEE ,  Johann ALSMEIER

IPC: H01L21/768 ,  H01L23/522 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L21/76805 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

公开(公告)号：US20170179152A1

公开(公告)日：2017-06-22

申请号：US15269041

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki TOYAMA ,  Yuki MIZUTANI ,  Hiroyuki OGAWA

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170125433A1

公开(公告)日：2017-05-04

申请号：US15174030

申请日：2016-06-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Hiroyuki TANAKA

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

公开(公告)号：US20240196612A1

公开(公告)日：2024-06-13

申请号：US18354283

申请日：2023-07-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro TOBIOKA ,  Masahiro YAEGASHI ,  Takayuki MAEKURA ,  Takaaki IWAI ,  Hiroyuki OGAWA

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

公开(公告)号：US20240179905A1

公开(公告)日：2024-05-30

申请号：US18352726

申请日：2023-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takayuki MAEKURA ,  Takaaki IWAI ,  Hiroyuki OGAWA ,  Koichi MATSUNO

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.