公开(公告)号：US20240153994A1

公开(公告)日：2024-05-09

申请号：US18500802

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Kazutaka YOSHIZAWA

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20240147730A1

公开(公告)日：2024-05-02

申请号：US18500721

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyokazu SHISHIDO ,  Kazutaka YOSHIZAWA ,  Dai IWATA ,  Hokuto KODATE

IPC: H10B43/40 ,  H10B41/40

CPC classification number: H10B43/40 ,  H10B41/40 ,  G11C16/08

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20240032299A1

公开(公告)日：2024-01-25

申请号：US18480855

申请日：2023-10-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA ,  Fumiaki TOYAMA

IPC: H10B43/40 ,  G11C16/04 ,  H10B43/35 ,  H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/43

CPC classification number: H10B43/40 ,  G11C16/0483 ,  H10B43/35 ,  H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/43

Abstract: A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a second peripheral circuit configured to control operation of a second set of electrical nodes of the three-dimensional memory array, where the second peripheral circuit is located at a different vertical level than the first peripheral circuit relative to the three-dimensional-memory array.

公开(公告)号：US20220109070A1

公开(公告)日：2022-04-07

申请号：US17063182

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Junko ONO ,  Yasuyuki AOKI ,  Kazutaka YOSHIZAWA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

公开(公告)号：US20170236835A1

公开(公告)日：2017-08-17

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Jin LIU ,  Kazuya TOKUNAGA ,  Marika GUNJI-YONEOKA ,  Matthias BAENNINGER ,  Hiroyuki KINOSHITA ,  Murshed CHOWDHURY ,  Jiyin XU ,  Dai IWATA ,  Hiroyuki OGAWA ,  Kazutaka YOSHIZAWA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20240072042A1

公开(公告)日：2024-02-29

申请号：US18500862

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Kazutaka YOSHIZAWA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823871 ,  H01L21/823878 ,  H01L28/60 ,  H01L29/42376

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20240063062A1

公开(公告)日：2024-02-22

申请号：US17821273

申请日：2022-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kouta ONOGI ,  Kazutaka YOSHIZAWA ,  Hokuto KODATE ,  Mitsuhiro TOGO ,  Takahito FUJITA

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/285 ,  H01L21/265 ,  H01L21/266 ,  H01L21/768 ,  H01L29/49 ,  H01L29/45 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/4933 ,  H01L29/45 ,  H01L23/535 ,  H01L27/088

Abstract: A transistor includes a first active region and a second active region separated by a semiconductor channel, a gate stack structure including a gate dielectric and a gate electrode overlying the semiconductor channel, a gate contact via structure overlying and electrically connected to the gate electrode and having a top surface located in a first horizontal plane, a first active-region contact via structure overlying and electrically connected to the first active region, and having a top surface located within a second horizontal plane that underlies the first horizontal plane, a first connection line structure contacting a top surface of the first active-region contact via structure, and a first connection via structure contacting a top surface of the first connection line structure and having a top surface within the first horizontal plane.

公开(公告)号：US20200295012A1

公开(公告)日：2020-09-17

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/768

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200091157A1

公开(公告)日：2020-03-19

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20190006381A1

公开(公告)日：2019-01-03

申请号：US15638672

申请日：2017-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

Abstract: A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.