公开(公告)号：US20220359690A1

公开(公告)日：2022-11-10

申请号：US17316015

申请日：2021-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dai IWATA ,  Hiroshi NAKATSUJI ,  Hiroyuki OGAWA ,  Eiichi FUJIKURA

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/07 ,  H01L21/8238 ,  H01L29/40

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

公开(公告)号：US20240258317A1

公开(公告)日：2024-08-01

申请号：US18631240

申请日：2024-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyokazu SHISHIDO ,  Hiroshi NAKATSUJI ,  Dai IWATA ,  Koichi MATSUNO

IPC: H01L27/092 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/76224 ,  H01L27/0207 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L27/0629

Abstract: A first field effect transistor includes a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion. The first active region includes a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction. The first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction. A maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.

公开(公告)号：US20220399447A1

公开(公告)日：2022-12-15

申请号：US17348305

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jun AKAIWA ,  Hiroshi NAKATSUJI ,  Masashi ISHIDA

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US20220416037A1

公开(公告)日：2022-12-29

申请号：US17362121

申请日：2021-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro TOGO ,  Hiroshi NAKATSUJI

IPC: H01L29/417 ,  H01L29/40

Abstract: A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.

公开(公告)号：US20220399448A1

公开(公告)日：2022-12-15

申请号：US17348328

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro TOGO ,  Jun AKAIWA ,  Hiroshi NAKATSUJI ,  Masashi ISHIDA

IPC: H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US20200295012A1

公开(公告)日：2020-09-17

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/768

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200091157A1

公开(公告)日：2020-03-19

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20190006381A1

公开(公告)日：2019-01-03

申请号：US15638672

申请日：2017-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

Abstract: A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.