公开(公告)号：US20200295012A1

公开(公告)日：2020-09-17

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/768

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20200091157A1

公开(公告)日：2020-03-19

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi NAKATSUJI ,  Yasuyuki AOKI ,  Shigeki SHIMOMURA ,  Akira INOUE ,  Kazutaka YOSHIZAWA ,  Hiroyuki OGAWA

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US20220109070A1

公开(公告)日：2022-04-07

申请号：US17063182

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Junko ONO ,  Yasuyuki AOKI ,  Kazutaka YOSHIZAWA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.