公开(公告)号：US20210375847A1

公开(公告)日：2021-12-02

申请号：US16886164

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell CHIBVONGODZE ,  Zhixin CUI ,  Rajdeep GAUTAM

IPC: H01L25/18 ,  H01L23/00 ,  G11C7/12 ,  G11C7/06 ,  H01L25/00

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US20210305384A1

公开(公告)日：2021-09-30

申请号：US16828129

申请日：2020-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Hardwell CHIBVONGODZE ,  Masatoshi NISHIKAWA

IPC: H01L29/423 ,  H01L27/11582 ,  H01L29/417 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.

公开(公告)号：US20200266182A1

公开(公告)日：2020-08-20

申请号：US16275668

申请日：2019-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Hardwell CHIBVONGODZE

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  G11C16/16 ,  G11C16/26

Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.

公开(公告)号：US20200098771A1

公开(公告)日：2020-03-26

申请号：US16142644

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Hardwell CHIBVONGODZE

IPC: H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.