公开(公告)号：US20190273088A1

公开(公告)日：2019-09-05

申请号：US15909073

申请日：2018-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Hiroshi MINAKATA ,  Keigo KITAZAWA ,  Yoshiyuki OKURA

IPC: H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/788 ,  H01L27/11582 ,  H01L23/528

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

公开(公告)号：US20200251479A1

公开(公告)日：2020-08-06

申请号：US16408722

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Masaaki HIGASHITANI ,  Masanori TSUTSUMI ,  Zhixin CUI

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.

公开(公告)号：US20200168623A1

公开(公告)日：2020-05-28

申请号：US16202713

申请日：2018-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Michiaki SANO ,  Ken OOWADA ,  Zhixin CUI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/8234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

公开(公告)号：US20190252403A1

公开(公告)日：2019-08-15

申请号：US16181721

申请日：2018-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michimoto KAMINAGA ,  Zhixin CUI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/40114 ,  H01L29/40117

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.

公开(公告)号：US20220285387A1

公开(公告)日：2022-09-08

申请号：US17192603

申请日：2021-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Zhixin CUI

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

公开(公告)号：US20210257379A1

公开(公告)日：2021-08-19

申请号：US16794563

申请日：2020-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Ippei YASUDA

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

公开(公告)号：US20200098780A1

公开(公告)日：2020-03-26

申请号：US16138001

申请日：2018-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Kiyohiko SAKAKIBARA ,  Shinsuke YADA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/423

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

公开(公告)号：US20220344362A1

公开(公告)日：2022-10-27

申请号：US17241321

申请日：2021-04-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Satoshi SHIMIZU

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.

公开(公告)号：US20210375847A1

公开(公告)日：2021-12-02

申请号：US16886164

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell CHIBVONGODZE ,  Zhixin CUI ,  Rajdeep GAUTAM

IPC: H01L25/18 ,  H01L23/00 ,  G11C7/12 ,  G11C7/06 ,  H01L25/00

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US20200286875A1

公开(公告)日：2020-09-10

申请号：US16291504

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio NISHIDA ,  Mitsuteru MUSHIGA ,  Zhixin CUI

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.