公开(公告)号：US20230413551A1

公开(公告)日：2023-12-21

申请号：US17807819

申请日：2022-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao CHEN ,  Shigehisa INOUE ,  Kazuto OHSAWA ,  Hisaya SAKAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L23/5283

Abstract: A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.

公开(公告)号：US20210351109A1

公开(公告)日：2021-11-11

申请号：US16868821

申请日：2020-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jo SATO ,  Masanori TSUTSUMI ,  Hisaya SAKAI

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/8234

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures extending through the alternating stack are formed. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer and the backside contact via structure are formed within the backside trench. A dielectric isolation trench is formed by removing a peripheral portion of an upper region of the backside contact via structure and an upper portion of the insulating spacer. A dielectric isolation spacer is formed in the dielectric isolation trench to prevent an electrical short between an upper portion of the backside contact via structure and the electrically conductive layers.

公开(公告)号：US20210210428A1

公开(公告)日：2021-07-08

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto OHSAWA ,  Kota FUNAYAMA ,  Hisaya SAKAI ,  Yoshitaka OTSU

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.