公开(公告)号：US20230413551A1

公开(公告)日：2023-12-21

申请号：US17807819

申请日：2022-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao CHEN ,  Shigehisa INOUE ,  Kazuto OHSAWA ,  Hisaya SAKAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L23/5283

Abstract: A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.

公开(公告)号：US20180019256A1

公开(公告)日：2018-01-18

申请号：US15332429

申请日：2016-10-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka AMANO ,  Takashi ARAI ,  Genta MIZUNO ,  Shigehisa INOUE ,  Naoki TAKEGUCHI ,  Takashi HAMAYA

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53266 ,  H01L27/11565 ,  H01L27/1157

Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

公开(公告)号：US20190252396A1

公开(公告)日：2019-08-15

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Hisakazu OTOI ,  Shigehisa INOUE ,  Yuki FUKUDA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/762

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/40114 ,  H01L29/40117

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

公开(公告)号：US20210327897A1

公开(公告)日：2021-10-21

申请号：US17090420

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki KASAI ,  Shigehisa INOUE ,  Tomohiro ASANO ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

公开(公告)号：US20200251489A1

公开(公告)日：2020-08-06

申请号：US16519092

申请日：2019-07-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Shigehisa INOUE ,  Tomohiro KUBO ,  James KAI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.

公开(公告)号：US20200020715A1

公开(公告)日：2020-01-16

申请号：US16242245

申请日：2019-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Yu UEDA ,  Tatsuya HINOUE ,  Shigehisa INOUE ,  Genta MIZUNO ,  Masanori TSUTSUMI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.