公开(公告)号：US11973123B2

公开(公告)日：2024-04-30

申请号：US17578177

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Kartik Sondhi

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/30

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US20240130137A1

公开(公告)日：2024-04-18

申请号：US18233628

申请日：2023-08-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik Sondhi ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani ,  Fei Zhou

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers. The discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers.

公开(公告)号：US12219776B2

公开(公告)日：2025-02-04

申请号：US17578199

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Kartik Sondhi

IPC: H10B51/20 ,  H01L23/48 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.