公开(公告)号：US20180366486A1

公开(公告)日：2018-12-20

申请号：US15626444

申请日：2017-06-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tsuyoshi HADA ,  Satoshi SHIMIZU ,  Kazuyo MATSUMOTO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A planar material layer stack including a lower etch stop dielectric layer, a sacrificial semiconductor layer, and an upper etch stop dielectric layer is formed over a source semiconductor layer on a substrate. An alternating stack of insulating layers and spacer material layers is formed. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. An array of memory stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the memory films. Source strap structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric fill material layer fills a remaining volume of the source cavity.