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    THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME
    1.
    发明公开
    THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20240206171A1

    公开(公告)日：2024-06-20

    申请号：US18352025

    申请日：2023-07-13

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA ,  Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

    IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

    CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

    Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

    THREE-DIMENSIONAL MEMORY DEVICE EMPLOYING DIRECT SOURCE CONTACT AND HOLE CURRENT DETECTION AND METHOD OF MAKING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE EMPLOYING DIRECT SOURCE CONTACT AND HOLE CURRENT DETECTION AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20190043830A1

    公开(公告)日：2019-02-07

    申请号：US15669243

    申请日：2017-08-04

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kiyohiko SAKAKIBARA ,  Satoshi SHIMIZU ,  Naoto NORIZUKI

    IPC: H01L25/065 ,  H05K7/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11568 ,  H01L49/02

    Abstract: A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTILEVEL DRAIN-SELECT ELECTRODES AND METHODS FOR FORMING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTILEVEL DRAIN-SELECT ELECTRODES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20220344266A1

    公开(公告)日：2022-10-27

    申请号：US17682466

    申请日：2022-02-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Akihiro TOBIOKA ,  Satoshi SHIMIZU

    IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers, memory opening fill structures vertically extending through the alternating stack, and drain-select-level contact via structures. A first one of the drain-select level contact structures directly contacts at least a first two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other. A second one of the drain-select level contact structures directly contacts at least a second two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other and which are located below the at least the first two of the drain-select-level electrically conductive layers.

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