公开(公告)号：US20170365613A1

公开(公告)日：2017-12-21

申请号：US15279959

申请日：2016-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Marika GUNJI-YONEOKA ,  Atsushi SUYAMA ,  Jayavel PACHAMUTHU ,  Tsuyoshi HADA ,  Daewung KANG ,  Murshed CHOWDHURY ,  James KAI ,  Hiro KINOSHITA ,  Tomoyuki OBU ,  Luckshitha Suriyasena LIYANAGE

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

公开(公告)号：US20180366486A1

公开(公告)日：2018-12-20

申请号：US15626444

申请日：2017-06-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tsuyoshi HADA ,  Satoshi SHIMIZU ,  Kazuyo MATSUMOTO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A planar material layer stack including a lower etch stop dielectric layer, a sacrificial semiconductor layer, and an upper etch stop dielectric layer is formed over a source semiconductor layer on a substrate. An alternating stack of insulating layers and spacer material layers is formed. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. An array of memory stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the memory films. Source strap structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric fill material layer fills a remaining volume of the source cavity.