公开(公告)号：US20220068954A1

公开(公告)日：2022-03-03

申请号：US17007761

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US20210098029A1

公开(公告)日：2021-04-01

申请号：US16589404

申请日：2019-10-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon KIM ,  Kwang-Ho KIM ,  Yuki MIZUTANI ,  Fumiaki TOYAMA

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures. Each metal pad is electrically connected to a respective bit line through a series connection of a respective pad-connection via structure, a respective contact-level metal interconnect, and a respective bit-line-connection via structure.

公开(公告)号：US20220068903A1

公开(公告)日：2022-03-03

申请号：US17007823

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Peter RABKIN

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US20220013518A1

公开(公告)日：2022-01-13

申请号：US17411635

申请日：2021-08-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Masaaki HIGASHITANI ,  Fumiaki TOYAMA ,  Akio NISHIDA

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US20200235090A1

公开(公告)日：2020-07-23

申请号：US16251954

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed CHOWDHURY ,  Kwang-Ho KIM ,  James KAI ,  Johann ALSMEIER

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/48 ,  H01L23/00 ,  G11C5/02

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

公开(公告)号：US20200357814A1

公开(公告)日：2020-11-12

申请号：US16404844

申请日：2019-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon KIM ,  Kwang-Ho KIM ,  Fumiaki TOYAMA

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions. Metal line structures connecting contact via structures can extend parallel to bit lines to provide electrical connections between word lines and underlying field effect transistors.

公开(公告)号：US20200066703A1

公开(公告)日：2020-02-27

申请号：US16669888

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Masaaki HIGASHITANI ,  Fumiaki TOYAMA ,  Akio NISHIDA

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US20190221557A1

公开(公告)日：2019-07-18

申请号：US16243469

申请日：2019-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Masaaki HIGASHITANI ,  Fumiaki TOYAMA ,  Akio NISHIDA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US20210225736A1

公开(公告)日：2021-07-22

申请号：US16747943

申请日：2020-01-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon KIM ,  Kwang-Ho KIM ,  Fumiaki TOYAMA

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

公开(公告)号：US20200243498A1

公开(公告)日：2020-07-30

申请号：US16261869

申请日：2019-01-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Kwang-Ho KIM ,  Johann ALSMEIER

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.