公开(公告)号：US20240206171A1

公开(公告)日：2024-06-20

申请号：US18352025

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA ,  Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20240206169A1

公开(公告)日：2024-06-20

申请号：US18351992

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20230164988A1

公开(公告)日：2023-05-25

申请号：US17664550

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5226

Abstract: A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

公开(公告)号：US20220208748A1

公开(公告)日：2022-06-30

申请号：US17134997

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Kwang-ho KIM

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.

公开(公告)号：US20220068954A1

公开(公告)日：2022-03-03

申请号：US17007761

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US20230164997A1

公开(公告)日：2023-05-25

申请号：US17664542

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier layer may be a dielectric blocking barrier layer.

公开(公告)号：US20220352104A1

公开(公告)日：2022-11-03

申请号：US17244387

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.

公开(公告)号：US20220310656A1

公开(公告)日：2022-09-29

申请号：US17373973

申请日：2021-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.

公开(公告)号：US20220246562A1

公开(公告)日：2022-08-04

申请号：US17167161

申请日：2021-02-04

Applicant: Sandisk Technologies LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

公开(公告)号：US20220093555A1

公开(公告)日：2022-03-24

申请号：US17542963

申请日：2021-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI ,  Rahul SHARANGPANI

IPC: H01L23/00

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.