公开(公告)号：US11575015B2

公开(公告)日：2023-02-07

申请号：US17348328

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro Togo ,  Jun Akaiwa ,  Hiroshi Nakatsuji ,  Masashi Ishida

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US12041770B2

公开(公告)日：2024-07-16

申请号：US17562888

申请日：2021-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masashi Ishida

IPC: H10B41/35 ,  G11C16/04 ,  H01L29/06 ,  H10B41/10 ,  H10B41/27

CPC classification number: H10B41/35 ,  G11C16/0483 ,  H01L29/0649 ,  H10B41/10 ,  H10B41/27

Abstract: A field effect transistor includes a source region embedded in a semiconductor material layer, a drain region embedded in the semiconductor material layer and laterally spaced from the source region by a channel, a gate stack including a gate dielectric and a gate electrode, a shallow trench isolation portion embedded in an upper portion of the semiconductor material layer and contacting the drain region and the gate stack, and a concave drain extension region continuously extending underneath the shallow trench isolation portion from a bottom surface of the gate dielectric to a bottom surface of the drain region.

公开(公告)号：US20230209821A1

公开(公告)日：2023-06-29

申请号：US17562888

申请日：2021-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masashi Ishida

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  G11C16/04 ,  H01L29/06

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  G11C16/0483 ,  H01L29/0649

Abstract: A field effect transistor includes a source region embedded in a semiconductor material layer, a drain region embedded in the semiconductor material layer and laterally spaced from the source region by a channel, a gate stack including a gate dielectric and a gate electrode, a shallow trench isolation portion embedded in an upper portion of the semiconductor material layer and contacting the drain region and the gate stack, and a concave drain extension region continuously extending underneath the shallow trench isolation portion from a bottom surface of the gate dielectric to a bottom surface of the drain region.

公开(公告)号：US11626496B2

公开(公告)日：2023-04-11

申请号：US17348305

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jun Akaiwa ,  Hiroshi Nakatsuji ,  Masashi Ishida

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.