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公开(公告)号：US11626496B2
公开(公告)日：2023-04-11
申请号：US17348305
申请日：2021-06-15
发明人： Jun Akaiwa , Hiroshi Nakatsuji , Masashi Ishida
IPC分类号： H01L29/417 , H01L29/78 , H01L29/40 , H01L29/45 , H01L27/092 , H01L21/8238 , H01L29/66
摘要： A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
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公开(公告)号：US10804284B2
公开(公告)日：2020-10-13
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/10 , H01L21/3105 , H01L21/02
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
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公开(公告)号：US11837601B2
公开(公告)日：2023-12-05
申请号：US17316079
申请日：2021-05-10
发明人： Jun Akaiwa , Dai Iwata , Hiroshi Nakatsuji , Eiichi Fujikura , Hiroyuki Ogawa
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/06 , H01L21/8234 , H01L23/522
CPC分类号： H01L27/088 , H01L21/82385 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L27/0629 , H01L27/0928
摘要： A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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公开(公告)号：US11575015B2
公开(公告)日：2023-02-07
申请号：US17348328
申请日：2021-06-15
发明人： Mitsuhiro Togo , Jun Akaiwa , Hiroshi Nakatsuji , Masashi Ishida
IPC分类号： H01L29/76 , H01L29/94 , H01L29/417 , H01L29/06 , H01L27/088 , H01L29/78 , H01L21/8234
摘要： A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
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公开(公告)号：US20220359501A1
公开(公告)日：2022-11-10
申请号：US17316079
申请日：2021-05-10
发明人： Jun Akaiwa , Dai Iwata , Hiroshi Nakatsuji , Eiichi Fujikura , Hiroyuki Ogawa
IPC分类号： H01L27/088 , H01L27/092 , H01L27/06 , H01L21/8234 , H01L21/8238 , H01L23/522
摘要： A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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6.发明申请公开(公告)号：US20190319040A1
公开(公告)日：2019-10-17
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L29/10 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
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公开(公告)号：US10256099B1
公开(公告)日：2019-04-09
申请号：US15916720
申请日：2018-03-09
发明人： Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/265 , H01L27/088 , H01L29/49 , H01L29/78 , H01L21/3213 , H01L21/308 , H01L29/66
摘要： A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first composite gate electrode containing a first vertical stack of a p-doped semiconductor gate electrode, a first interfacial dielectric layer, and a first metallic gate electrode. The second field effect transistor includes a second composite gate electrode containing a second vertical stack that includes an n-doped semiconductor gate electrode and a second metallic gate electrode. A second interfacial dielectric layer having a second thickness that is thinner than the first interfacial dielectric layer may, or may not, be present in the second composite gate electrode.
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