公开(公告)号：US11237729B1

公开(公告)日：2022-02-01

申请号：US17068955

申请日：2020-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Debasish Dwibedy ,  A Harihara Sravan ,  Nihal Singla ,  Muralikrishna Balaga

IPC: G06F3/06

Abstract: An inversion encoder is configured to receive a plurality of bytes of data for parallel output to a data bus; determine, in parallel, Hamming distances of neighboring pairs of bytes of the received plurality of bytes of data; for each neighboring pair of bytes of the received plurality of bytes, determine, in parallel, for each of the neighboring pairs of bytes, whether a respective Hamming distance satisfies a majority function; if a respective Hamming distance for a particular pair of bytes of the neighboring pairs of bytes satisfies the majority function: set an inversion bit for a second byte of the particular pair of bytes to be the opposite of an inversion bit for a first byte of the particular pair of bytes; invert, or forgo inverting, the second byte based on the inversion bit for the second byte; and provide the second byte for output to the data bus.

公开(公告)号：US10020059B1

公开(公告)日：2018-07-10

申请号：US15486168

申请日：2017-04-12

Applicant: SanDisk Technologies LLC

Inventor： Muralikrishna Balaga ,  Vinayak Ghatawade ,  Aditya Pradhan

IPC: G11C16/06 ,  G11C16/12 ,  H03K19/00

CPC classification number: G11C16/12 ,  G11C7/1057 ,  G11C8/08 ,  G11C16/08 ,  G11C16/24 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005

Abstract: A memory device includes an electrical line operably coupled to a plurality of memory cells, and a switchable impedance driver operably coupled to the electrical line. An electronic circuit includes a first driver having a first output impedance, and a second driver having a second output impedance that is less than the first output impedance. The first driver and the second driver are operably coupled in parallel to an output of the electronic circuit. The electronic circuit includes logic circuitry to enable the second driver during switching of a digital output of the driver. A method includes driving an output with both the first driver and the second driver when an input switches between logic levels, and disabling the second driver when the output reaches a desired logic level following the switch between logic levels of the input.