公开(公告)号：US20190051703A1

公开(公告)日：2019-02-14

申请号：US15672929

申请日：2017-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Hisakazu OTOI ,  Seje TAKAKI ,  Tuan PHAM

IPC: H01L27/24 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423

Abstract: A two-dimensional array of vertical field effect transistors is provided, which includes a one-dimensional array of ladder-shaped gate electrode lines. Each of the ladder-shaped gate electrode lines includes a pair of rail portions that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction and rung portions extending between the pair of rail portions along the second horizontal direction. The vertical field effect transistors include gate dielectrics located in each opening defined by a neighboring pair of rung portions, and vertical semiconductor channels laterally surrounded by a respective one of the gate dielectrics and extending along a vertical direction. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines of a three-dimensional ReRAM device.

公开(公告)号：US20190074441A1

公开(公告)日：2019-03-07

申请号：US15695225

申请日：2017-09-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shin KIKUCHI ,  Seje TAKAKI

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.

公开(公告)号：US20190103467A1

公开(公告)日：2019-04-04

申请号：US15720490

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seje TAKAKI ,  Jongsun SEL ,  Hisakazu OTOI ,  Chao Feng YEH

IPC: H01L29/417 ,  H01L27/02 ,  H01L27/11

Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.