公开(公告)号：US20190051703A1

公开(公告)日：2019-02-14

申请号：US15672929

申请日：2017-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Hisakazu OTOI ,  Seje TAKAKI ,  Tuan PHAM

IPC: H01L27/24 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423

Abstract: A two-dimensional array of vertical field effect transistors is provided, which includes a one-dimensional array of ladder-shaped gate electrode lines. Each of the ladder-shaped gate electrode lines includes a pair of rail portions that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction and rung portions extending between the pair of rail portions along the second horizontal direction. The vertical field effect transistors include gate dielectrics located in each opening defined by a neighboring pair of rung portions, and vertical semiconductor channels laterally surrounded by a respective one of the gate dielectrics and extending along a vertical direction. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines of a three-dimensional ReRAM device.

公开(公告)号：US20190006418A1

公开(公告)日：2019-01-03

申请号：US15635321

申请日：2017-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Mitsuteru MUSHIGA ,  Vincent SHIH ,  Akio NISHIDA ,  Tuan PHAM

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.

公开(公告)号：US20180108671A1

公开(公告)日：2018-04-19

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo YU ,  Jayavel PACHAMUTHU ,  Jongsun SEL ,  Tuan PHAM ,  Cheng-Chung CHU ,  Yao-Sheng LEE ,  Kensuke YAMAGUCHI ,  Masanori TERAHARA ,  Shuji MINAGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US20170373087A1

公开(公告)日：2017-12-28

申请号：US15195377

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitoshi ITO ,  Masaaki HIGASHITANI ,  Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

公开(公告)号：US20170373078A1

公开(公告)日：2017-12-28

申请号：US15195446

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM ,  Fumitoshi ITO ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/22 ,  H01L27/11519 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.