公开(公告)号：US20180108671A1

公开(公告)日：2018-04-19

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo YU ,  Jayavel PACHAMUTHU ,  Jongsun SEL ,  Tuan PHAM ,  Cheng-Chung CHU ,  Yao-Sheng LEE ,  Kensuke YAMAGUCHI ,  Masanori TERAHARA ,  Shuji MINAGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US20190103467A1

公开(公告)日：2019-04-04

申请号：US15720490

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seje TAKAKI ,  Jongsun SEL ,  Hisakazu OTOI ,  Chao Feng YEH

IPC: H01L29/417 ,  H01L27/02 ,  H01L27/11

Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.

公开(公告)号：US20190088717A1

公开(公告)日：2019-03-21

申请号：US15711075

申请日：2017-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chao Feng YEH ,  Jongsun SEL ,  Zhen CHEN

IPC: H01L27/24 ,  H01L45/00

Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

公开(公告)号：US20190051703A1

公开(公告)日：2019-02-14

申请号：US15672929

申请日：2017-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Hisakazu OTOI ,  Seje TAKAKI ,  Tuan PHAM

IPC: H01L27/24 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423

Abstract: A two-dimensional array of vertical field effect transistors is provided, which includes a one-dimensional array of ladder-shaped gate electrode lines. Each of the ladder-shaped gate electrode lines includes a pair of rail portions that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction and rung portions extending between the pair of rail portions along the second horizontal direction. The vertical field effect transistors include gate dielectrics located in each opening defined by a neighboring pair of rung portions, and vertical semiconductor channels laterally surrounded by a respective one of the gate dielectrics and extending along a vertical direction. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines of a three-dimensional ReRAM device.

公开(公告)号：US20190006418A1

公开(公告)日：2019-01-03

申请号：US15635321

申请日：2017-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Mitsuteru MUSHIGA ,  Vincent SHIH ,  Akio NISHIDA ,  Tuan PHAM

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.