公开(公告)号：US10403639B2

公开(公告)日：2019-09-03

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Orimoto ,  James Kai ,  Sayako Nagamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US20190027489A1

公开(公告)日：2019-01-24

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi ORIMOTO ,  James KAI ,  Sayako Najamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.