公开(公告)号：USRE49165E1

公开(公告)日：2022-08-09

申请号：US16906278

申请日：2020-06-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Masanori Tsutsumi ,  Shinsuke Yada ,  Sayako Nagamine ,  Johann Alsmeier

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex concave sidewall portions.

公开(公告)号：US10957680B2

公开(公告)日：2021-03-23

申请号：US16249423

申请日：2019-01-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shinsuke Yada ,  Masanori Tsutsumi ,  Sayako Nagamine ,  Yuji Fukano ,  Akio Nishida ,  Christopher J. Petti

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L29/10 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/36 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L29/788 ,  H01L29/51 ,  H01L29/167 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28

Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies. Semiconductor substrates may be removed from each memory die upon bonding to a pre-existing assembly.

公开(公告)号：US10943917B2

公开(公告)日：2021-03-09

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Makoto Koto ,  Sayako Nagamine ,  Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L21/762 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

公开(公告)号：US10403639B2

公开(公告)日：2019-09-03

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Orimoto ,  James Kai ,  Sayako Nagamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US11121149B2

公开(公告)日：2021-09-14

申请号：US16211387

申请日：2018-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Tanaka ,  Sayako Nagamine ,  Akihisa Sai

IPC: H01L27/11582 ,  H01L29/06 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/02

Abstract: An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

公开(公告)号：US10297610B2

公开(公告)日：2019-05-21

申请号：US15818061

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Shinsuke Yada ,  Akihisa Sai ,  Sayako Nagamine ,  Takashi Orimoto ,  Tong Zhang

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US11581049B2

公开(公告)日：2023-02-14

申请号：US17335909

申请日：2021-06-01

Applicant: SanDisk Technologies LLC

Inventor： Kazuki Isozumi ,  Parth Amin ,  Sayako Nagamine ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/10 ,  G11C29/52 ,  G11C16/08 ,  G11C29/12

Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

公开(公告)号：US20220383967A1

公开(公告)日：2022-12-01

申请号：US17335909

申请日：2021-06-01

Applicant: SanDisk Technologies LLC

Inventor： Kazuki Isozumi ,  Parth Amin ,  Sayako Nagamine ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/10 ,  G11C29/12 ,  G11C16/08 ,  G11C29/52

Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

公开(公告)号：US11417621B2

公开(公告)日：2022-08-16

申请号：US17113293

申请日：2020-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Masanori Tsutsumi ,  Sayako Nagamine

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11556

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

公开(公告)号：US10236300B2

公开(公告)日：2019-03-19

申请号：US15784549

申请日：2017-10-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Masanori Tsutsumi ,  Shinsuke Yada ,  Sayako Nagamine ,  Johann Alsmeier

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.