公开(公告)号：US10964715B2

公开(公告)日：2021-03-30

申请号：US16268132

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Manabu Kakazu ,  Takashi Yuda ,  Yuji Fukano

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L21/28

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

公开(公告)号：US12193228B2

公开(公告)日：2025-01-07

申请号：US17064834

申请日：2020-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Noriyuki Nagahata ,  Takashi Yuda ,  Ryousuke Itou

IPC: H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

公开(公告)号：US11171150B2

公开(公告)日：2021-11-09

申请号：US16295206

申请日：2019-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Yuda ,  Hiroyuki Kamiya

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/306 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel. The channel connection strap portion may be formed by a selective semiconductor growth from physically exposed semiconductor surfaces, and may provide enhanced electrical connection between the pedestal channel portion and the vertical semiconductor channel.