公开(公告)号：US11171150B2

公开(公告)日：2021-11-09

申请号：US16295206

申请日：2019-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Yuda ,  Hiroyuki Kamiya

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/306 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel. The channel connection strap portion may be formed by a selective semiconductor growth from physically exposed semiconductor surfaces, and may provide enhanced electrical connection between the pedestal channel portion and the vertical semiconductor channel.

公开(公告)号：US10354859B1

公开(公告)日：2019-07-16

申请号：US15920793

申请日：2018-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Kamiya ,  Shigehisa Inoue ,  Seiji Shimabukuro

IPC: H01L21/02 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L21/8229 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8232

Abstract: An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.