公开(公告)号：US12178040B2

公开(公告)日：2024-12-24

申请号：US17406463

申请日：2021-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryousuke Itou ,  Akihisa Sai ,  Kenzo Iizuka

IPC: H10B41/27 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H10B43/27 ,  H01L23/522

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

公开(公告)号：US12193228B2

公开(公告)日：2025-01-07

申请号：US17064834

申请日：2020-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Noriyuki Nagahata ,  Takashi Yuda ,  Ryousuke Itou

IPC: H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

公开(公告)号：US12101936B2

公开(公告)日：2024-09-24

申请号：US17523487

申请日：2021-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya Hinoue ,  Yusuke Mukae ,  Ryousuke Itou ,  Masanori Tsutsumi ,  Akio Nishida ,  Ramy Nashed Bassely Said

IPC: H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

公开(公告)号：US11532570B2

公开(公告)日：2022-12-20

申请号：US17174064

申请日：2021-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Genta Mizuno ,  Kenzo Iizuka ,  Satoshi Shimizu ,  Keisuke Izumi ,  Tatsuya Hinoue ,  Yujin Terasawa ,  Seiji Shimabukuro ,  Ryousuke Itou ,  Yanli Zhang ,  Johann Alsmeier ,  Yusuke Yoshida

IPC: H01L27/11556 ,  H01L23/00 ,  H01L27/11582 ,  H01L23/522

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

公开(公告)号：US12225720B2

公开(公告)日：2025-02-11

申请号：US17530861

申请日：2021-11-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryousuke Itou ,  Akihisa Sai ,  Kenzo Iizuka

IPC: H10B41/27 ,  H01L21/3213 ,  H01L21/768 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/532

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

公开(公告)号：US11018152B2

公开(公告)日：2021-05-25

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya Hinoue ,  Kengo Kajiwara ,  Ryousuke Itou ,  Naohiro Hosoda

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

公开(公告)号：US09754999B1

公开(公告)日：2017-09-05

申请号：US15240998

申请日：2016-08-18

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada ,  Yusuke Oda

IPC: H01L27/11551 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/2454 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/249 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

公开(公告)号：US09673257B1

公开(公告)日：2017-06-06

申请号：US15172483

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Akira Nakada ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/66 ,  H01L29/51 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/786 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.