公开(公告)号：US20230309319A1

公开(公告)日：2023-09-28

申请号：US18067998

申请日：2022-12-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jordan KATINE ,  Lei WAN ,  Tsai-Wei WU ,  Sanjay MEHTA

IPC: H10B61/00 ,  H10N50/80 ,  H10N50/01

CPC classification number: H01L27/224 ,  H01L43/02 ,  H01L43/12

Abstract: A device structure includes first electrically conductive lines, second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines, a two-dimensional array of magnetic tunnel junctions located between the first electrically conductive lines and the second electrically conductive lines, and a two-dimensional array of selector elements located in series with the two-dimensional array of magnetic tunnel junctions. Each of the magnetic tunnel junctions includes a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer, and has a respective pair of first tapered planar sidewalls laterally extending along a first horizontal direction and a respective pair of second tapered planar sidewalls laterally extending along a second horizontal direction.

公开(公告)号：US20220223649A1

公开(公告)日：2022-07-14

申请号：US17654762

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei WAN ,  Jordan KATINE ,  Tsai-Wei WU

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

公开(公告)号：US20210126052A1

公开(公告)日：2021-04-29

申请号：US16666967

申请日：2019-10-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei WAN ,  Jordan KATINE ,  Tsai-Wei WU

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A memory device includes a cross-point array of spin-torque transfer MRAM cells. First rail structures laterally extend along a first horizontal direction. Each of the first rail structures includes a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer. Second rail structures laterally extend along a second horizontal direction. Each of the second rail structures includes a second electrically conductive line that overlies the first rail structures. A two-dimensional array of pillar structures is located between a respective one of the first rail structures and a respective one of the second rail structures. Each of the pillar structures includes a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction.

公开(公告)号：US20220199686A1

公开(公告)日：2022-06-23

申请号：US17654768

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei WAN ,  Jordan KATINE ,  Tsai-Wei WU ,  Chu-Chen FU

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.