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公开(公告)号：US10804284B2
公开(公告)日：2020-10-13
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/10 , H01L21/3105 , H01L21/02
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
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公开(公告)号：US10770459B2
公开(公告)日：2020-09-08
申请号：US16227565
申请日：2018-12-20
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/768 , H01L21/308 , H01L29/08 , H01L29/423 , H01L27/11582
摘要： A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.
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3.发明申请公开(公告)号：US20190296012A1
公开(公告)日：2019-09-26
申请号：US16227565
申请日：2018-12-20
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/768 , H01L21/308 , H01L29/08 , H01L29/423
摘要： A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.
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4.发明申请公开(公告)号：US20190319040A1
公开(公告)日：2019-10-17
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L29/10 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
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