公开(公告)号：US20190199371A1

公开(公告)日：2019-06-27

申请号：US15854222

申请日：2017-12-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba ,  Shashi Kumar Shaw ,  Shrikrishna Nana Mehetre

IPC: H03M7/30 ,  H04L25/02 ,  G06F13/42 ,  H03M5/16 ,  H04L27/06

CPC classification number: H03M7/3055 ,  G06F13/426 ,  H03K19/017509 ,  H03K19/018521 ,  H03M5/16 ,  H04L25/0276 ,  H04L25/49 ,  H04L27/06

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

公开(公告)号：US10585999B2

公开(公告)日：2020-03-10

申请号：US15869484

申请日：2018-01-12

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba

IPC: G06F17/50

Abstract: Systems and methods for selecting die and package parasitic for an input-output (IO) power domain are described. In one embodiment, the method includes determining a minimum on-die decoupling capacitance based at least in part on a product of a number of simultaneously switching IOs of the die and a maximum instantaneous current of an IO; determining a maximum package inductance based at least in part on a maximum operating frequency of an IC and a target impedance of a power delivery network of the die, the IC package, and a printed circuit board (PCB); and determining a maximum die resistance based at least in part on preventing the maximum die resistance from exceeding a maximum static IR drop of the die.

公开(公告)号：US10560116B2

公开(公告)日：2020-02-11

申请号：US15854222

申请日：2017-12-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba ,  Shashi Kumar Shaw ,  Shrikrishna Nana Mehetre

IPC: H03M11/00 ,  H03M7/30 ,  H04L25/02 ,  G06F13/42 ,  H04L27/06 ,  H03M5/16 ,  H03K19/0185 ,  H04L25/49 ,  H03K19/0175

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.