公开(公告)号：US20190019747A1

公开(公告)日：2019-01-17

申请号：US15649337

申请日：2017-07-13

Applicant: Seagate Technology LLC

Inventor： Pritesh PAWASKAR ,  Yehuda Smooha ,  Shrikrishna Nana Mehetre

IPC: H01L23/50 ,  H01L23/498 ,  H01L27/02 ,  H01L23/00

Abstract: An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

公开(公告)号：US10560116B2

公开(公告)日：2020-02-11

申请号：US15854222

申请日：2017-12-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba ,  Shashi Kumar Shaw ,  Shrikrishna Nana Mehetre

IPC: H03M11/00 ,  H03M7/30 ,  H04L25/02 ,  G06F13/42 ,  H04L27/06 ,  H03M5/16 ,  H03K19/0185 ,  H04L25/49 ,  H03K19/0175

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

公开(公告)号：US10763205B2

公开(公告)日：2020-09-01

申请号：US15649337

申请日：2017-07-13

Applicant: Seagate Technology LLC

Inventor： Pritesh Pawaskar ,  Yehuda Smooha ,  Shrikrishna Nana Mehetre

IPC: H01L23/50 ,  H01L23/498 ,  H01L27/02 ,  H01L23/00

Abstract: An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

公开(公告)号：US20190199371A1

公开(公告)日：2019-06-27

申请号：US15854222

申请日：2017-12-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba ,  Shashi Kumar Shaw ,  Shrikrishna Nana Mehetre

IPC: H03M7/30 ,  H04L25/02 ,  G06F13/42 ,  H03M5/16 ,  H04L27/06

CPC classification number: H03M7/3055 ,  G06F13/426 ,  H03K19/017509 ,  H03K19/018521 ,  H03M5/16 ,  H04L25/0276 ,  H04L25/49 ,  H04L27/06

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.