公开(公告)号：US09142543B2

公开(公告)日：2015-09-22

申请号：US14172217

申请日：2014-02-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takashi Katakura ,  Hirofumi Harada ,  Yoshitsugu Hirose

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/0274 ,  H01L27/0288

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract translation: 提供具有较小面积的ESD保护电路。 ESD保护电路包括：P型扩散电阻器12，其一端连接到形成在N型阱中的输入端子11; 设置在扩散电阻器12和连接到电源端子的N型阱之间的二极管14; 漏极连接到扩散电阻器12的另一端的NMOS晶体管15; 以及形成在电源端子和接地端子之间的寄生二极管。