公开(公告)号：US09142543B2

公开(公告)日：2015-09-22

申请号：US14172217

申请日：2014-02-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takashi Katakura ,  Hirofumi Harada ,  Yoshitsugu Hirose

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/0274 ,  H01L27/0288

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract translation: 提供具有较小面积的ESD保护电路。 ESD保护电路包括：P型扩散电阻器12，其一端连接到形成在N型阱中的输入端子11; 设置在扩散电阻器12和连接到电源端子的N型阱之间的二极管14; 漏极连接到扩散电阻器12的另一端的NMOS晶体管15; 以及形成在电源端子和接地端子之间的寄生二极管。

公开(公告)号：US09136145B2

公开(公告)日：2015-09-15

申请号：US13846584

申请日：2013-03-18

Applicant: Seiko Instruments Inc.

Inventor： Hirofumi Harada

IPC: H01L21/58 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/58 ,  H01L23/49513 ,  H01L23/4952 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Provided is a semiconductor integrated circuit device having flexible pin arrangement. A semiconductor integrated circuit is bonded to a die pad with an insulating paste, and the potential of the die pad is fixed through a bonding wire from an Al pad provided on the surface of the semiconductor integrated circuit. In the case of a P-type semiconductor substrate, the die pad is set as a terminal other than a terminal having a minimum operating potential of the semiconductor integrated circuit.

Abstract translation: 提供了具有柔性引脚布置的半导体集成电路器件。 利用绝缘膏将半导体集成电路接合到管芯焊盘，并且通过接合线将焊盘的电位从设置在半导体集成电路的表面上的Al焊盘固定。 在P型半导体基板的情况下，将芯片焊盘设定为具有半导体集成电路的最小工作电位的端子以外的端子。

公开(公告)号：US09461038B2

公开(公告)日：2016-10-04

申请号：US14711589

申请日：2015-05-13

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi Harada

IPC: H01L21/20 ,  H01L27/06 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an insulated gate field effect transistor and a resistance circuit having a resistance element. The resistance element has a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film of silicon nitride formed on the first thin film so as to be wider than the resistance element, an intermediate insulating film of silicon oxide formed on the second thin film, a contact hole passing through the second thin film and provided in the intermediate insulating film at a depth reaching the first thin film, and a metal wiring formed in the contact hole. The insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.

Abstract translation: 半导体器件包括绝缘栅场效应晶体管和具有电阻元件的电阻电路。 电阻元件具有布置在设置在半导体衬底的表面上的隔离氧化膜上的第一薄膜，形成在第一薄膜上的第二氮化硅薄膜比电阻元件宽，中间绝缘膜 形成在第二薄膜上的氧化硅，通过第二薄膜并在到达第一薄膜的深度处设置在中间绝缘膜中的接触孔以及形成在接触孔中的金属布线。 绝缘栅场效应晶体管设置在由隔离氧化膜包围的半导体衬底的区域中。

公开(公告)号：US09791873B2

公开(公告)日：2017-10-17

申请号：US14805550

申请日：2015-07-22

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi Harada ,  Shinjiro Kato

IPC: H02M3/156 ,  H02M1/00 ,  G05F1/46

CPC classification number: G05F1/468 ,  G11C5/147

Abstract: A semiconductor integrated circuit device includes a PMOS output element having a source electrode connected to a power supply terminal and a drain electrode connected to an output voltage terminal from which an output voltage is supplied. A voltage dividing circuit has resistors for dividing the supplied output voltage to produce a divided voltage. A reference voltage circuit generates a reference voltage and has a memory element whose threshold voltage determines the reference voltage. The reference voltage circuit has a regulating input terminal connected to the memory element to change the threshold voltage of the memory element. An error amplifier is supplied with the divided voltage and the reference voltage to generate a voltage that is applied to a gate electrode of the PMOS output element. The voltage is amplified depending on a difference between the divided voltage and the reference voltage.

公开(公告)号：US09437669B2

公开(公告)日：2016-09-06

申请号：US14617572

申请日：2015-02-09

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi Harada ,  Masaru Akino

IPC: H01L27/10 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A semiconductor resistor circuit has resistor elements of a polycrystalline silicon thin film formed on an insulating film deposited on a semiconductor substrate. A high stress insulating film is formed on and covers the resistor elements and the insulating film exposed between the resistor elements. Metal wirings cover upper portions of the resistor elements. The high stress insulating film has a membrane stress that is higher than that of the metal wirings.

Abstract translation: 半导体电阻电路具有形成在沉积在半导体衬底上的绝缘膜上的多晶硅薄膜的电阻元件。 在电阻元件和电阻元件之间露出的绝缘膜上形成并覆盖高应力绝缘膜。 金属布线覆盖电阻元件的上部。 高应力绝缘膜的膜应力高于金属配线。