公开(公告)号：US20160071559A1

公开(公告)日：2016-03-10

申请号：US14844921

申请日：2015-09-03

Applicant: Seiko Instruments Inc.

Inventor： Makoto MITANI ,  Kotaro WATANABE

IPC: G11C7/10

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C7/106 ,  G11C7/22

Abstract: Provided is a data readout circuit capable of, even when a high voltage is applied during data read-out operation, preventing erroneous writing of the data and reading out the data correctly. The data readout circuit includes: a non-volatile storage element; a latch circuit including: an input inverter; an output inverter; and a MOS transistor; a first MOS transistor connected between the non-volatile storage element and the latch circuit; a second MOS transistor connected between the latch circuit and the first power supply terminal; a first bias circuit configured to bias a gate of the first MOS transistor; and a second bias circuit configured to bias the MOS transistor in the latch circuit, each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.

Abstract translation: 提供了一种数据读出电路，即使在数据读出操作期间施加高电压时，也能够防止数据的错误写入并正确地读出数据。 数据读出电路包括：非易失性存储元件; 锁存电路，包括：输入反相器; 输出变频器; 和MOS晶体管; 连接在非易失性存储元件和锁存电路之间的第一MOS晶体管; 连接在所述锁存电路和所述第一电源端子之间的第二MOS晶体管; 第一偏置电路，被配置为偏置所述第一MOS晶体管的栅极; 以及第二偏置电路，被配置为在所述锁存电路中偏置所述MOS晶体管，所述第一偏置电路和所述第二偏置电路中的每一个被配置为当所述非易失性存储元件中的数据被读出时输出预定的偏置电压。

公开(公告)号：US20170060096A1

公开(公告)日：2017-03-02

申请号：US15244178

申请日：2016-08-23

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Kazumi SAKUMOTO ,  Kotaro WATANABE ,  Minoru SANO

IPC: G04C3/14 ,  G04G3/00

CPC classification number: G04G19/12

Abstract: An electronic timepiece which can reduce currents flowing in a pull-down resistor or a pull-up resistor when a crown switch is turned on includes a first switch that is connected to a signal line, a second switch, and a one-shot pulse signal generation circuit. The first switch is inserted into the signal line. One end of the second switch is connected to the signal line on a rear stage of the first switch. The other end of the second switch is connected to a power source. The one-shot pulse signal generation circuit generates a one-shot pulse signal by using a reference clock signal. The second switch is controlled by the one-shot pulse signal.

Abstract translation: 当冠状开关接通时，可以减少在下拉电阻或上拉电阻中流动的电流的电子钟表包括连接到信号线，第二开关和单触发脉冲信号的第一开关 一代电路。 第一个开关插入信号线。 第二开关的一端连接到第一开关的后级上的信号线。 第二开关的另一端连接到电源。 单触发脉冲信号产生电路通过使用参考时钟信号产生单触发脉冲信号。 第二个开关由单触发脉冲信号控制。

公开(公告)号：US20140204720A1

公开(公告)日：2014-07-24

申请号：US14161235

申请日：2014-01-22

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Kotaro WATANABE ,  Makoto MITANI

IPC: G04G3/00 ,  H02M3/156

CPC classification number: G04G19/06 ,  G04C10/00 ,  G04G19/02

Abstract: There are provided a constant voltage circuit that features low current consumption and stable operation, and an analog electronic clock provided with the constant voltage circuit. The constant voltage circuit includes a differential amplifier circuit which is turned on/off by a predetermined signal and which controls the voltage of a gate of an output transistor on the basis of a reference voltage and a feedback voltage that are received, a switch circuit which is connected to an output terminal of the differential amplifier circuit and which is turned on/off by a predetermined signal, and a voltage holding circuit which is connected between the gate of the output transistor and a power supply terminal and which has a resistor and a capacitor connected in series. An analog electronic clock provided with the foregoing constant voltage circuit that supplies a voltage to at least an oscillation circuit and a frequency division circuit.

Abstract translation: 提供了具有低电流消耗和稳定运行的恒压电路，以及配有恒压电路的模拟电子时钟。 恒压电路包括通过预定信号导通/截止的差分放大电路，并根据接收到的基准电压和反馈电压来控制输出晶体管的栅极的电压;开关电路， 连接到差分放大器电路的输出端并通过预定信号导通/截止;以及电压保持电路，连接在输出晶体管的栅极和电源端之间，并具有电阻和 电容串联连接。 具有上述恒压电路的模拟电子时钟，其向至少一个振荡电路和分频电路提供电压。

公开(公告)号：US20130148444A1

公开(公告)日：2013-06-13

申请号：US13663952

申请日：2012-10-30

Applicant: Seiko Instruments Inc.

Inventor： Kotaro WATANABE ,  Makoto MITANI

IPC: G11C7/00

CPC classification number: G11C16/28

Abstract: There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T2 and a static electricity convergence time T1 are set so as to keep a relation of T1

Abstract translation: 公开了一种数据读取装置，其中非易失性存储元件的数据被反映在要调节的电路中，在打开电源或复位消除之后具有最小必需的延迟宽度，并且防止由静电引起的错误写入 。 另外设置延迟电路以在开启电源或产生复位消除的信号之后输出延迟的数据读取信号。 延迟时间T2和静电收敛时间T1被设定为保持T1

公开(公告)号：US20160065132A1

公开(公告)日：2016-03-03

申请号：US14836625

申请日：2015-08-26

Applicant: Seiko Instruments Inc.

Inventor： Kotaro WATANABE ,  Makoto MITANI

IPC: H03B5/36 ,  G04G19/00 ,  H03K3/012

CPC classification number: H03B5/364 ,  G04G3/00 ,  H03B5/30 ,  H03B5/32 ,  H03B5/366 ,  H03B2200/0062 ,  H03L5/00

Abstract: To provide a crystal oscillation circuit low in current consumption and stably short in oscillation start time. A crystal oscillation circuit is equipped with a crystal vibrator, a feedback resistor, a bias circuit, a constant voltage circuit, and an oscillation inverter configured by a constant current inverter. The oscillation inverter is configured so as to be controlled by currents based on input signals from the bias circuit and the crystal vibrator and driven by an output voltage of the constant voltage circuit.

Abstract translation: 提供消耗电流低，振荡开始时间短的晶体振荡电路。 晶体振荡电路配备有晶体振子，反馈电阻，偏置电路，恒压电路和由恒流逆变器构成的振荡反相器。 振荡反相器被配置为由基于来自偏置电路和晶体振子的输入信号的电流控制并由恒压电路的输出电压驱动。

公开(公告)号：US20140217950A1

公开(公告)日：2014-08-07

申请号：US14172627

申请日：2014-02-04

Applicant: Seiko Instruments Inc.

Inventor： Kotaro WATANABE ,  Makoto MITANI

IPC: H02M3/156 ,  H02P23/00

CPC classification number: H02P23/0095 ,  G04C10/00 ,  G04G19/06 ,  G05F1/613 ,  H02M2001/0006 ,  H02M2001/0035 ,  Y02B70/16

Abstract: There are provided a constant voltage circuit that outputs a stable constant voltage for an analog electronic clock, and an analog electronic clock featuring low current consumption and prolonged battery life. The constant voltage circuit has a first voltage holding circuit connected between the gate of an output transistor and an output terminal and a second voltage holding circuit connected between the gate of the output transistor and a ground terminal, and carries out control such that the second voltage holding circuit is enabled when the motor is operated.

Abstract translation: 提供了一个恒定电压电路，为模拟电子时钟输出稳定的恒定电压，以及具有低电流消耗和延长电池寿命的模拟电子时钟。 恒压电路具有连接在输出晶体管的栅极和输出端子之间的第一电压保持电路和连接在输出晶体管的栅极与接地端子之间的第二电压保持电路，并且进行控制，使得第二电压 保持电路在电机运行时使能。

公开(公告)号：US20140085996A1

公开(公告)日：2014-03-27

申请号：US14029251

申请日：2013-09-17

Applicant: Seiko Instruments Inc.

Inventor： Kotaro WATANABE ,  Makoto MITANI

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1063

Abstract: Provided is a readout circuit capable of detecting inversion of retained data caused by a noise, such as static electricity. The readout circuit is configured to retain opposing data in a first latch circuit and a second latch circuit in a readout period so as to be capable of detecting an anomaly of the retained data by making use of the fact that the data in the first latch circuit and the second latch circuit are inverted in the same direction due to a noise, such as static electricity.

Abstract translation: 提供一种能够检测由诸如静电之类的噪声引起的保留数据的反转的读出电路。 读出电路被配置为在读出期间将相对数据保存在第一锁存电路和第二锁存电路中，以便能够通过利用第一锁存电路中的数据来检测保留数据的异常 并且第二锁存电路由于诸如静电的噪声而在相同的方向上反转。

公开(公告)号：US20130249473A1

公开(公告)日：2013-09-26

申请号：US13784184

申请日：2013-03-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Makoto MITANI ,  Kotaro WATANABE

IPC: H02J7/00

CPC classification number: H02J7/0031 ,  H02J2007/0037

Abstract: The semiconductor device includes the charging system including: electric power generating unit for supplying electric power; electric power storing unit for storing electric power generated by the electric power generating unit; switch unit provided in a charging path for charging the electric power storing unit with the electric power generated by the electric power generating unit; a comparator driven by the electric power generated by the electric power generating unit for comparing a reference voltage and a stored voltage of the electric power storing unit; and a level converter provided between the comparator and the switch unit for, based on a result of a comparison made by the comparator, converting a level of a generated voltage to a level of the stored voltage and outputting a resultant to the switch unit.

Abstract translation: 该半导体装置包括：充电系统，包括：用于供电的发电单元; 蓄电单元，用于存储由所述发电单元产生的电力; 开关单元，设置在充电路径中，用于利用所述发电单元产生的电力对所述蓄电单元进行充电; 由所述发电单元产生的用于比较所述电力存储单元的参考电压和存储电压的电力驱动的比较器; 以及电平转换器，其设置在所述比较器和所述开关单元之间，用于基于由所述比较器进行的比较的结果，将所产生的电压的电平转换为所存储的电压的电平，并将结果输出到所述开关单元。

公开(公告)号：US20160126155A1

公开(公告)日：2016-05-05

申请号：US14927040

申请日：2015-10-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yoichi MIMURO ,  Kotaro WATANABE ,  Yukimasa MINAMI

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L21/563 ,  H01L23/562 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00

Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.

Abstract translation: 提供了一种倒装芯片安装的半导体器件，其中裂纹不太可能发展。 在划片区域上不存在氧化膜的情况下进行倒装芯片安装，以消除残留在划刻区域上的氧化膜与可能产生裂纹的硅衬底之间的界面。 结果，电路板，密封剂和硅衬底堆叠在半导体芯片的端部。

公开(公告)号：US20160018788A1

公开(公告)日：2016-01-21

申请号：US14797416

申请日：2015-07-13

Applicant: Seiko Instruments Inc.

Inventor： Makoto MITANI ,  Kotaro WATANABE

IPC: G04F5/04

CPC classification number: G04F5/04 ,  G04C10/00 ,  G04G3/00 ,  G04G19/06 ,  G04G19/08 ,  H02M3/1563

Abstract: To provide an analog electronic timepiece which prevents a crystal oscillation circuit from malfunctioning even if a battery voltage is lowered at motor loading. An analog electronic timepiece is equipped with a crystal vibrator, an oscillation circuit, a frequency division circuit, a constant voltage circuit, an output control circuit, and a motor. The analog electronic timepiece is configured in such a manner that the constant voltage circuit has a voltage holding circuit connected between a gate of an output transistor and a power supply terminal, and the oscillation circuit and the frequency division circuit are operated with a constant voltage generated by the constant voltage circuit as a power supply.

Abstract translation: 为了提供即使在电动机负载下电池电压降低的情况下也能防止晶体振荡电路发生故障的模拟电子钟表。 模拟电子钟表配备有晶体振子，振荡电路，分频电路，恒压电路，输出控制电路和电动机。 模拟电子钟表被配置成使得恒压电路具有连接在输出晶体管的栅极和电源端子之间的电压保持电路，并且以产生的恒定电压来操作振荡电路和分频电路 由恒压电路作为电源。