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公开(公告)号:US20190267496A1
公开(公告)日:2019-08-29
申请号:US16406228
申请日:2019-05-08
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Wonhwa LEE , Kwangwon LEE , Jaegil LEE
IPC: H01L29/868 , H01L29/417 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/872
Abstract: In a general aspect, a method can include forming a first pillar of a first conductivity type and a second pillar of a second conductivity type, alternately disposed with the first pillar. The second pillar can be in direct contact with the first pillar. The method can also include forming an implant of the second conductivity type in an upper portion of the second pillar. The implant can have a doping concentration that is higher than a doping concentration of a lower portion of the second pillar. The method can further include forming a Schottky metal layer having a first portion directly disposed on an upper surface of the first pillar and a second portion directly disposed on the implant along an upper surface of the second pillar. The first portion of the Schottky metal layer can be wider than the second portion of the Schottky metal layer.
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公开(公告)号:US20190074385A1
公开(公告)日:2019-03-07
申请号:US15697276
申请日:2017-09-06
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Wonhwa LEE , Kwangwon LEE , Jaegil LEE
IPC: H01L29/868 , H01L29/872 , H01L29/66 , H01L29/08
CPC classification number: H01L29/868 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/08 , H01L29/417 , H01L29/66143 , H01L29/872
Abstract: In a general aspect, a device can include a substrate, a first pillar of a first conductivity type, a second pillar of a second conductivity type, the first pillar and the second pillar being alternately disposed, and a metal layer having a first portion disposed on the first pillar and a second portion disposed on the second pillar. The first portion of the metal layer can be wider than the second portion of the metal layer.
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公开(公告)号:US20200098857A1
公开(公告)日:2020-03-26
申请号:US16141761
申请日:2018-09-25
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gary H. LOECHELT , Gordon M. GRIVNA , Jaegil LEE , MinKyung KO , Youngchul CHOI
IPC: H01L29/06 , H01L29/08 , H01L29/423 , H01L21/762 , H01L29/66 , H01L21/225 , H01L21/764 , H01L29/78
Abstract: A transistor device includes an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate. An isolation structure is disposed in a trench between the n-doped pillar and the p-doped pillar, and a source and a gate are disposed on the n-doped pillar. The isolation structure can include an air gap encapsulated in the trench by an oxide plug. The isolation structure can include an epi liner disposed on surfaces of the n-doped pillar and the p-doped pillar.
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