EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    1.
    发明申请

    公开(公告)号:US20180219038A1

    公开(公告)日:2018-08-02

    申请号:US15421505

    申请日:2017-02-01

    CPC classification number: H01L27/14618 H01L27/14634 H01L27/14636

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

    EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    2.
    发明公开

    公开(公告)号:US20240194710A1

    公开(公告)日:2024-06-13

    申请号:US18586731

    申请日:2024-02-26

    CPC classification number: H01L27/14618 H01L27/14634 H01L27/14636

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

    CURRENT SUBTRACTION CIRCUITRY
    3.
    发明申请

    公开(公告)号:US20190319619A1

    公开(公告)日:2019-10-17

    申请号:US15955379

    申请日:2018-04-17

    Inventor: Kyle THOMAS

    Abstract: An electronic device may include a sensing circuit and a current subtraction circuit. The sensing circuit may output first and second current signals. The current subtraction circuit may mirror the first and second current signals onto first and second current branches. The second current branch may be split into a first sub-path and a second sub-path. An amplifier may control the amount of current flowing through the second sub-path by forcing the current flowing through the first current branch and the current flowing through the first sub-path to be identical. Configured in this way, the current flowing through the second sub-path will be equal to the difference between the first and second current signals. The current flowing through the second sub-path may be optionally amplified using another current mirror.

    EDGE SEALS FOR SEMICONDUCTOR PACKAGES

    公开(公告)号:US20250151431A1

    公开(公告)日:2025-05-08

    申请号:US19013861

    申请日:2025-01-08

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

    EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    5.
    发明公开

    公开(公告)号:US20230261015A1

    公开(公告)日:2023-08-17

    申请号:US18305959

    申请日:2023-04-24

    CPC classification number: H01L27/14618 H01L27/14636 H01L27/14634

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

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