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    EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    1.
    发明公开
    EDGE SEALS FOR SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20240194710A1

    公开(公告)日：2024-06-13

    申请号：US18586731

    申请日：2024-02-26

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  Kyle THOMAS ,  David T. PRICE ,  Rusty WINZENREAD ,  Bruce GREENWOOD

    IPC: H01L27/146

    CPC classification number: H01L27/14618 ,  H01L27/14634 ,  H01L27/14636

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

    Stacking Single-Photon Avalanche Diodes and High Voltage Devices
    4.
    发明申请
    Stacking Single-Photon Avalanche Diodes and High Voltage Devices 有权

    公开(公告)号：US20250006766A1

    公开(公告)日：2025-01-02

    申请号：US18341825

    申请日：2023-06-27

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  Jaroslav PJENCAK ,  Radim SPETIK ,  Michael Gerard KEYES ,  Vincenzo SESTA ,  Moshe AGAM

    IPC: H01L27/146 ,  G01S7/481 ,  H01L23/00

    Abstract: Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.

    FIN TRANSISTORS WITH SEMICONDUCTOR SPACERS
    7.
    发明申请
    FIN TRANSISTORS WITH SEMICONDUCTOR SPACERS 有权

    公开(公告)号：US20220181462A1

    公开(公告)日：2022-06-09

    申请号：US17247212

    申请日：2020-12-03

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  Kevin Alexander STEWART ,  Peter MOENS ,  David T. PRICE ,  Derryl ALLMAN

    IPC: H01L29/49 ,  H01L29/24 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

    Abstract: In a general aspect, a transistor can include a fin having a proximal end and a distal end. The fin can include a dielectric portion longitudinally extending between the proximal end and the distal end, and a semiconductor layer disposed on the dielectric portion. The semiconductor layer can longitudinally extend between the proximal end and the distal end. The transistor can further include a source region disposed at the proximal end of the fin, and a drain region disposed at the distal end of the fin. The transistor can also include a gate dielectric layer disposed on a channel region of the semiconductor layer. The channel region can be disposed between the gate dielectric layer and the dielectric portion. The channel region can be longitudinally disposed between the source region and the drain region. The transistor can further include a conductive gate electrode disposed on the gate dielectric layer.

    BONDED SEMICONDUCTOR PACKAGE AND RELATED METHODS
    8.
    发明申请
    BONDED SEMICONDUCTOR PACKAGE AND RELATED METHODS 审中-公开

    公开(公告)号：US20200350271A1

    公开(公告)日：2020-11-05

    申请号：US16929335

    申请日：2020-07-15

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Thomas Fairfax LONG ,  Jeffrey Peter GAMBINO ,  Charles Alvah HILL

    IPC: H01L23/00 ,  H01L23/31

    Abstract: Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.

    EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    9.
    发明申请
    EDGE SEALS FOR SEMICONDUCTOR PACKAGES 有权

    公开(公告)号：US20250151431A1

    公开(公告)日：2025-05-08

    申请号：US19013861

    申请日：2025-01-08

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  Kyle THOMAS ,  David T. PRICE ,  Rusty WINZENREAD ,  Bruce Blair GREENWOOD

    IPC: H10F39/00

    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

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