公开(公告)号：US20250006766A1

公开(公告)日：2025-01-02

申请号：US18341825

申请日：2023-06-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Jaroslav PJENCAK ,  Radim SPETIK ,  Michael Gerard KEYES ,  Vincenzo SESTA ,  Moshe AGAM

IPC: H01L27/146 ,  G01S7/481 ,  H01L23/00

Abstract: Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.