公开(公告)号：US20210175265A1

公开(公告)日：2021-06-10

申请号：US16949228

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Marc Allen SULFRIDGE ,  Anne DEIGNAN ,  Nader JEDIDI ,  Michael Gerard KEYES

IPC: H01L27/146 ,  H01L31/107

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, multiple rings of isolation structures may be formed around the SPAD. An outer deep trench isolation structure may include a metal filler such as tungsten and may be configured to absorb light. The outer deep trench isolation structure therefore prevents crosstalk between adjacent SPADs. Additionally, one or more inner deep trench isolation structures may be included. The inner deep trench isolation structures may include a low-index filler to reflect light and keep incident light in the active area of the SPAD.

公开(公告)号：US20220367534A1

公开(公告)日：2022-11-17

申请号：US17302836

申请日：2021-05-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

IPC: H01L27/146

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

公开(公告)号：US20240321924A1

公开(公告)日：2024-09-26

申请号：US18673521

申请日：2024-05-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/1464

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

公开(公告)号：US20240055537A1

公开(公告)日：2024-02-15

申请号：US18493996

申请日：2023-10-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Marc Allen SULFRIDGE ,  Anne DEIGNAN ,  Nader JEDIDI ,  Michael Gerard KEYES

IPC: H01L31/02 ,  H01L27/146 ,  H01L31/055 ,  H01L31/107 ,  H01L31/0232 ,  G02B3/06

CPC classification number: H01L31/02027 ,  H01L27/14605 ,  H01L31/055 ,  H01L31/107 ,  H01L27/14643 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14649 ,  H01L31/02327 ,  G02B3/06 ,  H01L27/1463 ,  H01L27/1464 ,  H04N25/63

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, multiple rings of isolation structures may be formed around the SPAD. An outer deep trench isolation structure may include a metal filler such as tungsten and may be configured to absorb light. The outer deep trench isolation structure therefore prevents crosstalk between adjacent SPADs. Additionally, one or more inner deep trench isolation structures may be included. The inner deep trench isolation structures may include a low-index filler to reflect light and keep incident light in the active area of the SPAD.

公开(公告)号：US20250006766A1

公开(公告)日：2025-01-02

申请号：US18341825

申请日：2023-06-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Jaroslav PJENCAK ,  Radim SPETIK ,  Michael Gerard KEYES ,  Vincenzo SESTA ,  Moshe AGAM

IPC: H01L27/146 ,  G01S7/481 ,  H01L23/00

Abstract: Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.

公开(公告)号：US20240145504A1

公开(公告)日：2024-05-02

申请号：US18051600

申请日：2022-11-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Rick Carlton JEROME ,  David T. PRICE ,  Michael Gerard KEYES ,  Anne DEIGNAN

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643

Abstract: A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.