公开(公告)号：US20200066838A1

公开(公告)日：2020-02-27

申请号：US16111931

申请日：2018-08-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Moshe AGAM

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/761

Abstract: Systems and methods of the disclosed embodiments include a semiconductor device structure having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.

公开(公告)号：US20190043856A1

公开(公告)日：2019-02-07

申请号：US15669579

申请日：2017-08-04

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Thierry YAO ,  Mark GRISWOLD ,  Weize CHEN

IPC: H01L27/07 ,  H01L27/088 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/861

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US20180315747A1

公开(公告)日：2018-11-01

申请号：US16004718

申请日：2018-06-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Bruce GREENWOOD ,  Sallie HOSE ,  Agajan SUWHANOV

IPC: H01L27/02 ,  H01L21/265 ,  H01L21/762 ,  H01L29/739 ,  H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/76224 ,  H01L23/535 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/7396

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.

公开(公告)号：US20250006766A1

公开(公告)日：2025-01-02

申请号：US18341825

申请日：2023-06-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Jaroslav PJENCAK ,  Radim SPETIK ,  Michael Gerard KEYES ,  Vincenzo SESTA ,  Moshe AGAM

IPC: H01L27/146 ,  G01S7/481 ,  H01L23/00

Abstract: Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.

公开(公告)号：US20190148368A1

公开(公告)日：2019-05-16

申请号：US16244911

申请日：2019-01-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Thierry YAO ,  Mark GRISWOLD ,  Weize CHEN

IPC: H01L27/07 ,  H01L29/861 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US20190088554A1

公开(公告)日：2019-03-21

申请号：US16180819

申请日：2018-11-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Ladislav Seliga ,  Thierry Coffi Herve Yao ,  Jaroslav Pjencák ,  Gary H. Loechelt

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/761 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

公开(公告)号：US20210125879A1

公开(公告)日：2021-04-29

申请号：US16832671

申请日：2020-03-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Moshe AGAM ,  Thierry Coffi Herve YAO

IPC: H01L21/8238 ,  H01L21/266

Abstract: Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.

公开(公告)号：US20210125878A1

公开(公告)日：2021-04-29

申请号：US16832624

申请日：2020-03-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Thierry Coffi Herve YAO ,  Moshe AGAM

IPC: H01L21/8238 ,  H01L21/266

Abstract: Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.

公开(公告)号：US20170062610A1

公开(公告)日：2017-03-02

申请号：US14837228

申请日：2015-08-27

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Ladislav SELIGA ,  Thierry Coffi Herve YAO ,  Jaroslav PJENCÁK ,  Gary H. LOECHELT

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/761 ,  H01L21/823412 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Abstract translation: 电子器件可以包括具有主表面的半导体层，与主表面相邻的漂移区域，与漂移区域相邻并且与漂移区域相比更深地延伸到半导体层中的漏极区域， 主表面，覆盖漏极区域的绝缘层，以及延伸穿过绝缘层到漏极区域的接触。 在一个实施例中，漏极区域可以包括沉降片区域，其允许在过电压事件期间发生裸露区域的体破坏，其中体积击穿发生在漂移区域外部，并且在特定实施例中，远离浅沟槽隔离 结构或其他敏感结构。

公开(公告)号：US20140225178A1

公开(公告)日：2014-08-14

申请号：US14258260

申请日：2014-04-22

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Thierry Coffi Herve YAO ,  Skip Shizhen LIU

IPC: H01L23/525 ,  H01L29/78

CPC classification number: H01L23/5252 ,  H01L27/101 ,  H01L27/11206 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.

Abstract translation: 电子设备可以包括非易失性存储单元，其中非易失性存储单元可以包括基板，存取晶体管，读晶体管和反熔丝元件。 每个访问和读取晶体管可以包括至少部分在衬底内的源极/漏极区域，覆盖衬底的栅极电介质层和覆盖栅极电介质层的栅电极。 反熔丝部件可以包括至少部分位于衬底内的第一电极，覆盖衬底的反熔丝电介质层和覆盖反熔丝电介质层的第二电极。 反熔丝组件的第二电极可以耦合到存取晶体管的源极/漏极区域和读取晶体管的栅极电极之一。 在一个实施例中，反熔丝部件可以是晶体管结构的形式。 电子器件可以使用单个多晶硅工艺形成。