公开(公告)号：US20210193847A1

公开(公告)日：2021-06-24

申请号：US17191173

申请日：2021-03-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaroslav PJENCAK ,  Moshe AGAM ,  Johan Camiel Julia JANSSENS

IPC: H01L29/861 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

公开(公告)号：US20190043856A1

公开(公告)日：2019-02-07

申请号：US15669579

申请日：2017-08-04

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Thierry YAO ,  Mark GRISWOLD ,  Weize CHEN

IPC: H01L27/07 ,  H01L27/088 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/861

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US20200066838A1

公开(公告)日：2020-02-27

申请号：US16111931

申请日：2018-08-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Moshe AGAM

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/761

Abstract: Systems and methods of the disclosed embodiments include a semiconductor device structure having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.

公开(公告)号：US20250006766A1

公开(公告)日：2025-01-02

申请号：US18341825

申请日：2023-06-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Jaroslav PJENCAK ,  Radim SPETIK ,  Michael Gerard KEYES ,  Vincenzo SESTA ,  Moshe AGAM

IPC: H01L27/146 ,  G01S7/481 ,  H01L23/00

Abstract: Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.

公开(公告)号：US20190148368A1

公开(公告)日：2019-05-16

申请号：US16244911

申请日：2019-01-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Thierry YAO ,  Mark GRISWOLD ,  Weize CHEN

IPC: H01L27/07 ,  H01L29/861 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US20250149377A1

公开(公告)日：2025-05-08

申请号：US18500320

申请日：2023-11-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaroslav PJENCAK ,  Jan HYBL ,  Dusan POSTULKA ,  Juraj JARINA ,  David LYSACEK

IPC: H01L21/762

Abstract: A semiconductor substrate includes a handle wafer, an oxide layer formed on the handle wafer, and a device layer formed or disposed on the oxide layer. The device layer includes a first epitaxial silicon layer bonded to the oxide layer formed on the handle wafer, a layer of compensated silicon crystalline material formed or disposed on the first epitaxial silicon layer, and a second epitaxial silicon layer formed on the layer of compensated silicon crystalline material. The compensated silicon crystalline material includes a Czochralski silicon substrate.

公开(公告)号：US20220209008A1

公开(公告)日：2022-06-30

申请号：US17139748

申请日：2020-12-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize CHEN ,  Mark GRISWOLD ,  Jaroslav PJENCAK

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.