公开(公告)号：US07888272B2

公开(公告)日：2011-02-15

申请号：US11609747

申请日：2006-12-12

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC分类号： H01L21/318

CPC分类号： H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

摘要翻译： 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

公开(公告)号：US20080138998A1

公开(公告)日：2008-06-12

申请号：US11609747

申请日：2006-12-12

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC分类号： H01L21/31

CPC分类号： H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

摘要翻译： 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

公开(公告)号：US07486534B2

公开(公告)日：2009-02-03

申请号：US11297529

申请日：2005-12-08

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming Shang Chen

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming Shang Chen

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

摘要翻译： 一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体 并且设置成与第一行导体相邻并且与第二行导体相邻。 阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

公开(公告)号：US08183106B2

公开(公告)日：2012-05-22

申请号：US11460216

申请日：2006-07-26

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

摘要翻译： 一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。 因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。 此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

公开(公告)号：US20080026527A1

公开(公告)日：2008-01-31

申请号：US11460216

申请日：2006-07-26

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

摘要翻译： 一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。 因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。 此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

公开(公告)号：US07067374B2

公开(公告)日：2006-06-27

申请号：US10911959

申请日：2004-08-05

申请人： Tzung Ting Han ,  Yin Jen Chen ,  Ming Shang Chen

发明人： Tzung Ting Han ,  Yin Jen Chen ,  Ming Shang Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

摘要： Dual spacer structures are fabricated such that sidewall spacers in a cell region are thinner than sidewall spacers in a periphery region. The fabricating method of memory includes forming a stop layer over the first semiconductor feature and the second semiconductor feature in cell region and periphery region. A spacer layer is formed over the stop layer in the periphery region. The spacer layer is patterned to form a spacer on a sidewall of the second semiconductor feature. An etching process is performed to form a resultant spacer on an interior sidewall of the opening between first semiconductor features. The stop layer on top surfaces of the first and second semiconductor features is removed.

摘要翻译： 制造双间隔物结构，使得细胞区域中的侧壁间隔物比周边区域中的侧壁间隔物薄。 存储器的制造方法包括在单元区域和外围区域中的第一半导体特征和第二半导体特征之上形成停止层。 在周边区域中的停止层上形成间隔层。 图案化间隔层以在第二半导体特征的侧壁上形成间隔物。 执行蚀刻工艺以在第一半导体特征之间的开口的内侧壁上形成合成的间隔物。 去除第一和第二半导体特征的顶表面上的停止层。

公开(公告)号：US07889556B2

公开(公告)日：2011-02-15

申请号：US12690582

申请日：2010-01-20

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07668010B2

公开(公告)日：2010-02-23

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20100120210A1

公开(公告)日：2010-05-13

申请号：US12690582

申请日：2010-01-20

申请人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20090213656A1

公开(公告)日：2009-08-27

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C11/34 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。