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公开(公告)号：US20180033681A1
公开(公告)日：2018-02-01
申请号：US15553008
申请日：2016-02-05
发明人： Osamu ISHIKAWA , Masahiro KATO
IPC分类号： H01L21/762 , H01L21/265 , H01L23/00
CPC分类号： H01L21/76254 , H01L21/26506 , H01L21/3226 , H01L24/29 , H01L24/83 , H01L27/12 , H01L2224/29193 , H01L2224/83031 , H01L2224/83896 , H01L2924/01014
摘要： A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.
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公开(公告)号：US20160233107A1
公开(公告)日：2016-08-11
申请号：US15022846
申请日：2014-10-27
发明人： Masahiro KATO
IPC分类号： H01L21/324 , H01L21/673 , H01L21/67
CPC分类号： H01L21/324 , H01L21/67109 , H01L21/67306
摘要： A method for heat treatment of a plurality of semiconductor wafers horizontally placed on a supporting member coated with SiC in a vertical heat treatment furnace includes performing heat treatments while switching the supporting member and a heat treatment condition such that the supporting member is continuously used in a heat treatment under either one of a first condition and a second condition for a certain period of time and then continuously used in a heat treatment under the other condition for a certain period of time, wherein the heat treatment under the first condition is performed at 1000° C. or higher in an atmosphere containing a rare gas and not containing oxygen, and the heat treatment under the second condition is performed at 1000° C. or higher in an atmosphere containing oxygen and not containing a rare gas. As a result, slip dislocation can be inhibited.
摘要翻译： 在垂直热处理炉中水平放置在涂覆有SiC的支撑构件上的多个半导体晶片的热处理方法包括在切换支撑构件的同时执行热处理和热处理条件，使得支撑构件连续地用于 在第一条件和第二条件中的任何一个下进行一段时间的热处理，然后在另一条件下在一定时间内连续使用热处理，其中第一条件下的热处理在1000 在含有稀有气体且不含氧的气氛中，在第二条件下的热处理在含有氧气且不含有稀有气体的气氛中在1000℃以上进行。 结果，可以抑制滑脱位错。
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公开(公告)号：US20180136143A1
公开(公告)日：2018-05-17
申请号：US15573058
申请日：2016-03-09
发明人： Masahiro KATO
CPC分类号： G01N21/9501 , G01N21/94 , G01N21/956 , G01N2201/06113
摘要： A method for evaluating a semiconductor wafer includes detecting semiconductor wafer LPDs as an examination sample in two measurement modes, performing size classification of the LPDs, calculating a distance between detection coordinates and a relative angle in the two measurement modes, presetting determination criteria to determine each LPD as a foreign matter or killer defect in accordance with each classified size, detecting semiconductor wafer LPDs as an evaluation target in the two measurement modes, performing size classification of the LPDs as the evaluation target, calculating a distance between detection coordinates and a relative angle of the evaluation target, and classifying the LPDs detected on a surface of the evaluation target into the killer defect and the foreign mater based on a result of the calculation and the determination criteria. The method enables classifying all LPDs from which quantitative size information cannot be provided, into the killer defect and foreign matter.
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公开(公告)号：US20160197007A1
公开(公告)日：2016-07-07
申请号：US14910080
申请日：2014-07-15
发明人： Isao YOKOKAWA , Masahiro KATO
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： A method of producing a bonded wafer in which wafers each having a cutout portion are used as a bond wafer and a base wafer, and either or both of settings of an ion implanter with which ions are implanted and conditions of the ion implantation are adjusted in the step of implanting the ions such that a cutout portion of either or both of the bond wafer and the base wafer after bonding is located at within a range of 0±30° or 180±30° from a position at which separation of the bond wafer begins in the step of separating the bond wafer. This method can inhibit the occurrence of large fault defect that may be generated on a surface of a thin film right after the separation, when a thin film such as an SOI layer is formed by the ion implantation separation method.
摘要翻译： 一种制造接合晶片的方法，其中使用具有切口部分的晶片作为接合晶片和基底晶片，并且将离子注入的离子注入机和离子注入条件中的任一个或两个设置调整为 注入离子的步骤使得接合之后的接合晶片和基底晶片中的任一个或两者的切口部分位于距离键的分离位置0±30°或180±30°的范围内 晶片从分离接合晶片的步骤开始。 当通过离子注入分离法形成诸如SOI层的薄膜时，该方法可以抑制在分离之后薄膜的表面上可能产生的大的故障缺陷的发生。
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