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公开(公告)号：US20170047258A1
公开(公告)日：2017-02-16
申请号：US15305989
申请日：2015-02-25
发明人： Tsuyoshi Ohtsuki
CPC分类号： H01L22/14 , H01L21/02 , H01L23/66 , H01L27/12 , H01L27/1203
摘要： An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface state density and a leakage power upon application of radio-frequency thereon, or converting the interface state density to a resistance followed by previously determining a relationship between the converted resistance and the leakage power; measuring an interface state density of the evaluation target SOI substrate to determine the interface state density or a resistance converted from the interface state density; evaluating a leakage power of the evaluation target SOI substrate from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the interface state density and the leakage power, or from a resistance converted from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the resistance and leakage power.
摘要翻译： SOI衬底评估方法包括：在测量SOI衬底上形成器件，并且预先在其上施加射频之后确定接口状态密度和漏电功率之间的关系，或者将接口状态密度转换为先前的电阻 确定转换的电阻和泄漏功率之间的关系; 测量评估对象SOI衬底的界面状态密度，以确定界面态密度或从界面态密度转换的电阻; 根据确定的界面状态密度与泄漏功率之间的关系，或从测量的界面状态密度转换得到的电阻，根据所测定的评价对象物SOI SOI衬底的界面状态密度，评价评价对象物SOI SOI衬底的漏电功率 基于所确定的电阻和泄漏功率之间的关系来评估目标SOI衬底。
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公开(公告)号：US09780006B2
公开(公告)日：2017-10-03
申请号：US15305989
申请日：2015-02-25
发明人： Tsuyoshi Ohtsuki
CPC分类号： H01L22/14 , H01L21/02 , H01L23/66 , H01L27/12 , H01L27/1203
摘要： An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface state density and a leakage power upon application of radio-frequency thereon, or converting the interface state density to a resistance followed by previously determining a relationship between the converted resistance and the leakage power; measuring an interface state density of the evaluation target SOI substrate to determine the interface state density or a resistance converted from the interface state density; evaluating a leakage power of the evaluation target SOI substrate from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the interface state density and the leakage power, or from a resistance converted from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the resistance and leakage power.
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公开(公告)号：US09935021B2
公开(公告)日：2018-04-03
申请号：US14890687
申请日：2014-04-14
发明人： Tsuyoshi Ohtsuki
CPC分类号： H01L22/14 , H01L22/12 , H01L29/0688
摘要： A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.
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公开(公告)号：US09748151B2
公开(公告)日：2017-08-29
申请号：US15117537
申请日：2015-02-23
发明人： Tsuyoshi Ohtsuki , Hiroshi Takeno
IPC分类号： H01L21/66 , H01L21/324 , G01N23/225 , H01L21/265 , H01L21/268 , H01L21/322
CPC分类号： H01L22/24 , G01N23/2254 , G01N2223/3106 , G01N2223/6116 , H01L21/26513 , H01L21/2686 , H01L21/322 , H01L21/324 , H01L22/12
摘要： The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.
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公开(公告)号：US11248306B2
公开(公告)日：2022-02-15
申请号：US17052562
申请日：2019-04-02
发明人： Tsuyoshi Ohtsuki , Masaro Tamatsuka
摘要： An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.
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6.发明授权公开(公告)号：US10886129B2
公开(公告)日：2021-01-05
申请号：US16318223
申请日：2017-07-03
IPC分类号： H01L21/02 , H01L21/265 , H01L21/20 , H01L29/78
摘要： A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
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