公开(公告)号：US20090146759A1

公开(公告)日：2009-06-11

申请号：US11965744

申请日：2007-12-28

申请人： SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

发明人： SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

IPC分类号： H01P5/12

CPC分类号： H01P5/12 ,  H05K1/0246 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

摘要： A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal via a main transmission line, a second node coupled to the first node via a first branch transmission line, a first receiving terminal coupled to the first node via a second branch transmission line, a third node coupled to the second node via a third branch transmission line, and a second receiving terminal coupled to the second node via a fourth branch transmission line. The second branch transmission line is longer than the first transmission line, and a first resistor is connected in the second branch transmission line. The third branch transmission line is longer than the fourth branch transmission line, and a second resistor is connected in the third branch transmission line.

摘要翻译： 用于多个负载的电路拓扑包括驱动终端，经由主传输线耦合到驱动终端的第一节点，经由第一分支传输线耦合到第一节点的第二节点，经由第一节点经由 第二分支传输线，经由第三分支传输线耦合到第二节点的第三节点，以及经由第四分支传输线耦合到第二节点的第二接收终端。 第二分支传输线比第一传输线长，并且第一电阻器连接在第二分支传输线路中。 第三分支传输线比第四分支传输线长，并且第二电阻器连接在第三分支传输线路中。

公开(公告)号：US20090108956A1

公开(公告)日：2009-04-30

申请号：US11955409

申请日：2007-12-13

申请人： SHOU-KUO HSU ,  HSIAO-CHUAN TU

发明人： SHOU-KUO HSU ,  HSIAO-CHUAN TU

IPC分类号： H03H7/48 ,  H03H7/38

CPC分类号： G06F13/4086

摘要： A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal and a second node via a first branch transmission line, a first receiving terminal which is a test point configured to detect errors of the circuit topology coupled to the first node via a second branch transmission line, a second and a third receiving terminal respectively coupled to the second node via a third branch transmission line and a fourth branch transmission line, wherein the difference between the length of the second branch transmitting line and that of the third branch transmitting line, and the difference between the length of the third branch transmitting line and that of the fourth branch transmitting line are greater than the product of a transmission speed and a rise time of the signal, and a first resistor is connected in the third branch transmission line.

摘要翻译： 用于多个负载的电路拓扑包括驱动终端，耦合到驱动终端的第一节点和经由第一分支传输线的第二节点，第一接收终端，其被配置为检测耦合到所述驱动终端的电路拓扑的错误 第一分支传输线，第二和第三接收终端，分别经由第三分支传输线和第四分支传输线耦合到第二节点，其中第二分支传输线的长度与 第三分支传输线，第三分支传输线的长度与第四分支传输线的长度之间的差大于传输速度和信号的上升时间的乘积，并且第一电阻器连接到 第三分支传输线。

公开(公告)号：US20080116994A1

公开(公告)日：2008-05-22

申请号：US11838238

申请日：2007-08-14

申请人： SHOU-KUO HSU ,  CHIA-NAN PAI ,  HSIAO-CHUAN TU

发明人： SHOU-KUO HSU ,  CHIA-NAN PAI ,  HSIAO-CHUAN TU

IPC分类号： H03H7/38

CPC分类号： H05K1/0246 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10022

摘要： A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

摘要翻译： 提供了多个负载的电路拓扑。 在一个实施例中，电路拓扑包括驱动终端（50），第一节点（A），第一接收终端（10）和第二接收终端（20）。 驱动终端经由主传输线（11）耦合到第一节点，第一节点经由第一分支传输线（13）和第二分支传输线（12）分别耦合到第一和第二接收终端。 第一电阻器（R 2）安装在第二分支传输线上，信号经由主传输线从驱动端到达第二接收端的距离，第二分支传输线大于信号从 所述驱动终端经由所述主发送和所述第一分支传输线路发送到所述第一接收终端。

公开(公告)号：US20120095716A1

公开(公告)日：2012-04-19

申请号：US13195853

申请日：2011-08-02

申请人： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： G06F19/00

CPC分类号： G01R31/3627 ,  G01R31/2834 ,  G01R31/2837

摘要： A method for modulating multiple-instruments and multiple-sensors using an electronic device. The electronic device controls an instrument to measure the working parameters of an object, and controls a sensor to detect the working temperature of the object. By comparing the working parameters against a predefined range, and comparing the working temperature against a predefined temperature value, the electronic device determines whether the instrument and the sensor need to be modulated. If any of the working parameters is not within the predefined range or if the working temperature is greater than the predefined temperature value, the electronic device controls the instrument and the sensor to be modulated by using a modulation transfer function and a predetermined direction.

摘要翻译： 一种使用电子设备调制多仪器和多传感器的方法。 电子设备控制仪器来测量物体的工作参数，并控制传感器以检测物体的工作温度。 通过将工作参数与预定义范围进行比较，并将工作温度与预定义的温度值进行比较，电子设备确定仪器和传感器是否需要调制。 如果任何工作参数不在预定范围内，或者如果工作温度大于预定温度值，则电子设备通过使用调制传递函数和预定方向来控制仪器和传感器的调制。

公开(公告)号：US20110301923A1

公开(公告)日：2011-12-08

申请号：US12962838

申请日：2010-12-08

申请人： WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/509

摘要： A simulation system and method for generating equivalent circuits compatible with HSPICE reads data corresponding to N-port network system format in a storage device, and obtains S-parameter matrixes from the N-port network system. S-parameters in the S-parameter matrix that satisfy passivity are checked, and an interpolation algorithm to supplement S-parameters with passivity when some S-parameters not satisfy passivity is performed. Numbers of pole-residue, times for recursion and a tolerant system error of a rational function are generated for determining S-parameters. A rational function matrix composed of S-parameters is generated by performing a vector fitting algorithm, and an equivalent circuit is generated compatible with HSPICE format based on the generated rational function matrix.

摘要翻译： 用于产生与HSPICE兼容的等效电路的仿真系统和方法在存储设备中读取对应于N端口网络系统格式的数据，并且从N端口网络系统获得S参数矩阵。 检查满足被动性的S参数矩阵中的S参数，并且执行当某些S参数不满足被动时的用于补充具有被动性的S参数的插值算法。 产生极点残差数，递归次数和合理函数的容错系统误差，用于确定S参数。 通过执行向量拟合算法生成由S参数组成的合理函数矩阵，并且基于生成的有理函数矩阵生成与HSPICE格式兼容的等效电路。

公开(公告)号：US20110051793A1

公开(公告)日：2011-03-03

申请号：US12633895

申请日：2009-12-09

申请人： PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  CHIEN-HUNG LIU ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  CHIEN-HUNG LIU ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： H04B17/00

CPC分类号： H04B17/0085 ,  H04B17/21 ,  H04B17/23 ,  H04B17/327 ,  H04L1/0668

摘要： A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.

摘要翻译： 用于多输入多输出（MIMO）天线系统的性能评估系统从输入设备接收模拟参数，并相应地模拟MIMO天线系统。 还提供了一种方法，当通过MIMO天线系统传输一系列射频（RF）信号时，进一步评估模拟MIMO天线系统的性能，并且在用于评估的显示装置上显示MIMO天线系统的性能分析结果 的模拟MIMO天线系统的性能。

公开(公告)号：US20090166058A1

公开(公告)日：2009-07-02

申请号：US12042348

申请日：2008-03-05

申请人： YING-TSO LAI ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： YING-TSO LAI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/00

CPC分类号： H05K1/0216 ,  H05K2201/09027 ,  H05K2201/093

摘要： A printed circuit board (PCB) includes a power layer having a base portion, and at least two extending portions. The at least two extending portions are extended from edges near at least one corner of the base portion for preventing the PCB from forming constructive interferences and lowering the resonance magnitude thereof.

摘要翻译： 印刷电路板（PCB）包括具有基部的功率层和至少两个延伸部分。 至少两个延伸部分从靠近基部的至少一个拐角处的边缘延伸，以防止PCB形成结构性干扰并降低其共振幅度。

公开(公告)号：US20090102535A1

公开(公告)日：2009-04-23

申请号：US11967036

申请日：2007-12-29

申请人： CHUN-JEN CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： CHUN-JEN CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： G06F1/04

CPC分类号： G06F1/06 ,  G06F1/10

摘要： A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2.

摘要翻译： 用于多个负载的时钟信号电路包括时钟发生器和M个负载。 时钟发生器包括输出具有相同频率的时钟信号的N个时钟发生器引脚。 N个时钟发生器引脚都连接到连接点。 连接点分别通过M个发送线路连接到M个负载，其中M大于N，M和N分别为大于2的整数。

公开(公告)号：US20120197583A1

公开(公告)日：2012-08-02

申请号：US13290143

申请日：2011-11-07

申请人： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  PO-CHUAN HSIEH ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  PO-CHUAN HSIEH ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： G06F19/00

CPC分类号： G01R31/2801 ,  G01R31/2812 ,  G01R31/2834

摘要： A method of testing a printed circuit board (PCB) acquires test points from a wiring diagram of the PCB. Frequency domain tested items for each test point and a standard value of each frequency domain tested item are preset. A distance between a preset fiducial point and each test point is computed to create a testing order of the test points according to the distances. The frequency domain tested items of each test point are computed according to the testing order. A pass or a failure of each test point is displayed according to a determination of if each of the computed frequency domain tested items within the corresponding standard value, and a test result of the PCB is output according to the passes or the failures.

摘要翻译： 测试印刷电路板（PCB）的方法从PCB接线图获取测试点。 每个测试点的频域测试项目和每个频域测试项目的标准值都是预设的。 计算预设基准点与每个测试点之间的距离，以根据距离创建测试点的测试顺序。 每个测试点的频域测试项目根据测试顺序计算。 根据是否根据通过或故障输出每个计算出的频域测试项目在相应的标准值内以及PCB的测试结果的确定来显示每个测试点的通过或失败。

公开(公告)号：US20120032385A1

公开(公告)日：2012-02-09

申请号：US12981544

申请日：2010-12-30

申请人： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YUNG-CHIEH CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YUNG-CHIEH CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： B25B5/06

CPC分类号： B25B11/00 ,  B25B1/2421 ,  B25J15/106

摘要： A clamping mechanism for holding a workpiece includes an end executor, a driving member, and a contact member detachably mounted on the end executor. The end executor includes a plurality of claws arranged in matrix. The contact member includes a mounting board and a plurality of contact sleeves corresponding to the claws. The driving member is capable of driving the mounting board, moving the contact sleeves to extend the claws, and hold the workpiece.

摘要翻译： 用于保持工件的夹持机构包括端部执行器，驱动构件和可拆卸地安装在端部执行器上的接触构件。 末端执行器包括排列成矩阵的多个爪。 接触构件包括安装板和对应于爪的多个接触套筒。 驱动构件能够驱动安装板，移动接触套以延伸爪并且保持工件。