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    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    1.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230282603A1

    公开(公告)日：2023-09-07

    申请号：US17855241

    申请日：2022-06-30

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Sang Hyun SUNG ,  Hyun Soo SHIN ,  Kang Sik CHOI

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

    CPC分类号： H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1434

    摘要： A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.

    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210366919A1

    公开(公告)日：2021-11-25

    申请号：US17014370

    申请日：2020-09-08

    申请人： SK hynix Inc.

    发明人： Sang Hyun SUNG ,  Jin Ho KIM ,  Sung Lae OH

    IPC分类号： H01L27/11539 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528

    摘要： A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING PAGE BUFFERS
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING PAGE BUFFERS 有权

    公开(公告)号：US20210217478A1

    公开(公告)日：2021-07-15

    申请号：US16897140

    申请日：2020-06-09

    申请人： SK hynix Inc.

    发明人： Sung Lae OH

    IPC分类号： G11C16/14 ,  G11C16/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    摘要： A semiconductor memory device includes at least two transistors, each including a gate that traverses, in a first direction, an active region of a first substrate defined by an isolation layer, and junction regions disposed in the active region on opposite sides of the gate, and coupled to a memory cell array through a bit line; and a plurality of contacts, coupled respectively to the junction regions, that pass through a dielectric layer that covers the transistor. Among the plurality of contacts, a contact coupled to a junction region to which an erase voltage is loaded is disposed at a center portion of the active region in the first direction, and a contact coupled to a junction region to which the erase voltage is not loaded is disposed at an edge portion of the active region in the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210036005A1

    公开(公告)日：2021-02-04

    申请号：US16723711

    申请日：2019-12-20

    申请人： SK hynix Inc.

    发明人： Sung Lae OH

    IPC分类号： H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    摘要： A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160133642A1

    公开(公告)日：2016-05-12

    申请号：US14694829

    申请日：2015-04-23

    申请人： SK hynix Inc.

    发明人： Jae Eun JEON ,  Sung Lae OH

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565

    摘要： A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

    摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括：形成在半导体衬底上的存储单元结构; 形成在所述半导体衬底中的沟道部分; 形成为穿过所述存储单元结构的通孔; 形成在所述通孔的侧壁上的第一通道区域; 以及形成在所述通孔的中心部分并且与所述第一沟道区间隔开的第二沟道区域，其中所述第一沟道区域和所述第二沟道区域中的每一个耦合到所述沟道部分。